jss@sjuvax.UUCP (J. Shapiro) (06/23/85)
This may have come up before, and I suspect that I already know the answer, but maybe someone out there who has seen it in their hands can tell me for sure. In the manuals, I see no indication as to whether traps/interrupts are processed in user mode or supervisor mode. This is important, as if such things are handled in supervisor mode and one is clever about using traps (which one has to be for some security), then one can remove all of the worries about interrupt routines from the user address space in a system using an MMU by placing these routines in the system space and using the A24 bit that the MMU gives as one of the decoding lines for handling things. What's the verdict? My guess is that these things are handled in supervisor mode. If I missed the reference, would someone be kind enough to point it out to me? Thank you, Jonathan S. Shapiro
mark@nsc-pdc.UUCP (Mark Nudelman) (06/26/85)
> In the manuals, I see no indication as to whether traps/interrupts are > processed in user mode or supervisor mode. Traps/interrupts are indeed processed in supervisor mode. My reference: 32000 Instruction Set Manual, section 6.2: "General Interrupt/Trap Sequence": "1. Adjustment of Registers. .... A copy of the PSR is made, and the PSR is then set to reflect Supervisor Mode and selection of the Interrupt Stack." Mark Nudelman nsc!nsc-pdc!mark National Semiconductor tektronix!reed!nsc-pdc!mark
jack@boring.UUCP (07/01/85)
From "Series 32000 Instruction Set Reference Manual", Section 6.2 (General Interrupt/Trap Sequence): ... the PSR is then set to reflect Supervisor Mode, and the selection of the Interrupt Stack. It is kind of logical, too. I've never seen a machine that didn't switch to supervisor mode on an interrupt (ok, on the PDP-11 you can choose, but still.....) -- Jack Jansen, jack@mcvax.UUCP The shell is my oyster.
geoff@tolerant.UUCP (Geoffrey G. Peck) (07/02/85)
Interrupts and traps cause the processor to switch to supervisor state, at which point exception (interrupt or trap) processing proceeds as per chapter 6 in the Series 32000 Instruction Set Reference Manual (June 1984). Unfortunately, this rev of the manual doesn't contain much of the useful information on memory management and protection that the older rev did.