[net.micro.16k] Pre-fetch

doug@terak.UUCP (Doug Pardee) (07/15/85)

According to the specs on the NS32016:

  The one exception to [the page fault interrupt] sequence occurs if
  the aborted bus cycle was on an instruction prefetch.  If so, it is
  not yet certain that the aborted prefetched code is to be executed.
  Instead of causing an interrupt, the CPU only aborts the bus cycle,
  and stops prefetching.  If the information in the Instruction Queue
  runs out, meaning that the instruction will actually be executed,
  the ABT interrupt will occur, in effect aborting the instruction
  which was being fetched.

[Edited version of original posting -- for the folks on net.micro.16k]

> The symptoms were that under certain circumstances the system would
> hang due to a memory fault while in the kernel. The system we use
> is 68000 based with a 4-segment memory management unit. While in
> supervisor state the MMU is essentially disabled and the processor
> has access to all of physical memory.
> 
> It turned out that a routine for a driver was being relocated to the
> absolute end of physical memory, such that the last two bytes of
> memory contained an RTS (return from subroutine). When this
> instruction was executed the fault occurred because the 68K prefetches
> 2 to 4 bytes ahead of where it's executing. The prefetch was into
> nonexistent memory, hence the external logic produced the fault.
> This is a classic problem with pipelined systems.
-- 
Doug Pardee -- Terak Corp. -- !{ihnp4,seismo,decvax}!noao!terak!doug
               ^^^^^--- soon to be CalComp

thomson@uthub.UUCP (Brian Thomson) (07/18/85)

Yes, the 32016 does properly handle (i.e. ignore) page fault and
protection traps on prefetches, but it still isn't quite perfect.
We have seen a 32016 continue to prefetch after partially executing
an SVC instruction, such that it uses the old user-mode PC for
the prefetch address but does the accesses in system mode.
This can be a problem if the system-space address is, eg., a device
register or if the page is valid but mapped to nonexistent memory.
-- 
		    Brian Thomson,	    CSRI Univ. of Toronto
		    {linus,ihnp4,uw-beaver,floyd,utzoo}!utcsrgv!uthub!thomson