jnw@mcnc.UUCP (John White) (11/21/85)
Here is some info on the 32332. The NS32332-15 is National's new 32-bit data 32-bit address chip. It is like the 32032, but can go at 15Mhz, has a 20byte instruction queue, and has some internal improvements like the addition of a barrel shifter. The bus has multiplexed address and data, uses a 4 clock bus cycle, and has about 3cycles-50ns address-to-data on read. The chip is in an 85 pin grid array. Displacements on memory reference instructions can be +/- 64bytes, +/- 8Kbyte, or +/- 512Mbyte. This is short of the full 4Gbyte address space. Register indirect can get at the full 4Gbyte, of course. The 32332 supports the NS32081 and NS32C381 floating coprocessors, and the NS32082 and NS32C382 MMU. I didn't get any info on the 381 or 382, and I don't know what their status is. The 082 MMU doesn't seem to allow more than 24bit addresses. There is a hint that the 382 allows 4kbyte as well as 512byte pages. Of course, you can use your own MMU. The bus allows a special burst mode when reading instructions. If the processor wants to read the next instruction location, it will signal a burst request. If the memory acknowledges the request, the processor reads in data every 2 clocks without sending out addresses in between. Thus, reading n dwords requires 2+2n clocks. Wait states can be added, of course. A burst will stop at a 16byte boundry, so at most 4 reads will occur. Dynamic ram chips usually support reading several bits from a row in rapid succession, so burst mode reads can be supported with ordinary Dram chips. National didn't send me anything about instruction execution times, so I have no idea how fast it is. I find this annoying. (National claims 2 to 3 times faster than the 32032 and about 3MIPS.) Disclaimer: Read the above info at your own risk.