sehai@ucbcad.UUCP (Sehat Sutardja) (07/04/85)
*** REPLACE THIS LINE WITH YOUR MESSAGE *** While working on a research project on A/D (Analog to Digital) converters, I came out with a new approach of doing A/D conversion in CMOS technology. The difference of my approach to others is that mine would provide very high differential linearity even in the presence of large component missmatches. Unfortunately, the integral linearity is heavily depended on the component accuracies. Presently a 13 bits of differential linearity and 10 bits of integral linearity is feasible using a supply voltage of 5 volt only. The integral linearity is actually can be improved by self-calibration techniques, but I'd rather not use them here. (well, actually there was another approach which will give high differential linearity. However , none of the things that I've seen so far have integral linearity of more of 8 bits because of the use of resistor string. Of course this only applies to non calibrated/trimmed circuits.) When fully optimized, the conversion speed would be around 300,000 samples a second. Furthermore, because of the absence of calibration/trimming circuitry, all of the above goodies can be integrated in less than 1500 square mils of silicon area for the analog portion of the A/D. The digital portion is basically consisted of successive approximation registers and control circuitry, and therefore would be rather small as well. Now my question is that who wants to use this kind of A/D? Is the above A/D good enough to be used in Digital Subscriber Loop echo canceller? Any pointers would be very much appreciated. Sehat Sutardja sehai@ucbcad