fjh@bentley.UUCP (FJ Hirsch) (08/28/84)
@This is for you who don't have ARPA access.@
@Thanks to Bill Croft for mailing this to me.@
HARDWARE FOR APPLEBUS - ETHERNET GATEWAY
Bill Croft and Nick Veizades
Stanford SUMEX project.
1. INTRODUCTION
The gateway is a multibus system consisting of 3 cards:
"SUN" CPU board, 8 or 10 MHz, 256K RAM; in other words, the
cheapest 68K board you can find; several companies make these,
ours are from Forward Technology. You don't need DMA access
or anything fancy.
INTERLAN NI3210 10mb ethernet card. This has onboard memory, so DMA
is not needed on the processor. The Intel 82586 ethernet chip
does automatic buffer chaining of packets.
SUMEX applebus card. This is described below; it contains about
6 chips and can be wirewrapped in an afternoon.
Other hardware required:
5 slot multibus backplane; Electronics Solution's work well.
Power supply; small switchers run cool.
Ethernet tranceiver (we use TCL), and cable.
Ribbon cable from CPU (50 cond) to two ribbon DB-25 connectors;
these are the console and downline load serial lines.
Applebus tap and mini-DIN connectorized cable (from Apple).
2. SUMEX APPLEBUS CARD
2.1 PARTS
ARTEC (phone 415-592-2740) "multibus multipurpose interface board" ($165).
This board comes with the bus buffering and control logic all setup.
All you basically have to do is connect up your data IO lines and chip select.
ZYLOG Z8530 SCC; serial communications controller.
AMD 26LS32B; quad differential line receiver.
AMD 26LS30; dual differential tri-stateable driver.
DB-9, PC board mount, female.
7492; divide by six.
DIP pullup resistor pack (Beckman B98-1-R6.8K) 15 resistors.
XTAL, 22.1184 MHz; this is a "standard" frequency found in most stores.
Single package TTL oscillator, OR:
74S04; clock "oscillator".
2 1K resistors.
100 pf capacitor.
68 pf capacitor.
2.2 WIRING: OSCILLATOR
If you don't use a single package oscillator, this simple circuit
acts as one: (you might run the output though a couple more spare
inverters in the S04 to further "clean it up")
----\/\----- ----\/\-----
| 1K | 68p | 1K |
| |\ | | |\ |
| | \ | | | | | \ |
---| \O---|--| |--|---| \O--|----
| | / | | | / |
| |/ |/ |
| 100p X |
| | | |X| 22.1184|
|----| |-----------|X|--------|
| | |X|
X
2.3 WIRING: 7492 (divide by six)
from pin to pin
OSC 22.1184 MHz B input 1
gnd gnd 10
+5 Vcc 5
gnd reset inputs 6,7
Qd output 8 SCC PCLK 20
The PCLK is derived as follows: 22.1184 MHz divided by 6 gives
3.67864 MHz; this is connected to the SCC PCLK, RTxCA, and RTxCB.
In the digital phase lock loop mode, the SCC divides PCLK by 16
to get the FM0 sample rate: 3.67864 / 16 = 230400 bits per second.
2.4 WIRING: Z8530 SCC
from pin to pin
gnd gnd 31
+5 Vcc 9
7492 output 8 PCLK 20
PCLK 20 RTxCA,RTxCB 12,28
board DOUT 0 thru 7 board DIN 0 thru 7
board DOUT/IN 0 D0 40
board DOUT/IN 1 D1 1
board DOUT/IN 2 D2 39
board DOUT/IN 3 D3 2
board DOUT/IN 4 D4 38
board DOUT/IN 5 D5 3
board DOUT/IN 6 D6 37
board DOUT/IN 7 D7 4
pullup on each data line D0-D7 1,2,3,4,37,38,39,40
board BRD\ board DOUTE\
board BRD\ RD\ 36
board BWR\ board DINE\
board BWR\ WR\ 35
board BEN\ CE\ 33
pullup INTACK\ 8
pullup IEI 7
INT\ 5 board INT4\
board buffered INT4\ board multibus 37
board ADR0 A/B\ 34
board ADR1 D/C\ 32
TxDA 15 LS30 in A 2
RTSA\ 17 LS30 enb B\ 3
LS32B out A 3 RxDA 13
2.5 WIRING: 26LS32B receiver
from pin to pin
DB9 8 A in + 2
DB9 9 A in - 1
A out 3 SCC RxDA 13
gnd enable\ 12
gnd gnd 8
+5 Vcc 16
2.6 WIRING: 26LS30 driver
from pin to pin
SCC TxDA 15 A in 2
SCC RTSA\ 17 B enb\ 3
out A 15 DB9 4
out B 14 DB9 5
gnd mode 4
gnd gnd 5
+5 Vcc 1
2.7 WIRING: other board straps and switches
S1 - IO MAP
S2 - 0110 0000 0000; sets board address to 0x1f6000
S3 - all bits of address significant
ACK DELAY: XACK to CCLK*6
Copyright (C) 1984 Stanford Univ. SUMEX project.
May be used but not sold without permission.
--
<*> Fred Hirsch <*> AT&T Bell Laboratories <*> ihnp4!bentley!fjh <*>