info-vlsi@ucbvax.ARPA (09/21/84)
From: Doug Freyburger <DOUG@JPL-VLSI.ARPA>
A while ago I posted a request for information on functional testers.
I was suprised at how little information is available out there on them. It
seems that most people only have Tek DAS 9100's. Some people seem only to
want a DAS. That suprised me a lot since the DAS has so few channels. Few
people have ever heard of the Stanford MEDIUM machine, and even then it is
barely more than a rumor.
The only testers out there that seem in range of what I am looking for
are the Stanford MEDIUM and the Terak tester. If anyone has manuals on-line
for these, I'd like a copy. Are they Q-bus, IEEE-488, RS-232 interfaced? Is
there a good software kernal that goes with them?
What I am looking for is very many pins, 64 minumim and expanible,
that will work in the 1-4Mhz range. Anyone willing to fund a project to make
one? It may actually come down to cutting a proposal to do that. I think I
can make a simple design for Q-bus that will be under $20K per unit after the
prototype.
>From: Carl.Ebeling@CMU-CS-UNH.ARPA
>
>The tester that we use here at CMU is a home brewed version. It
>consists of a 68000 (running the popeye kernal) connected to a set of
>custom chips we designed and built here that allows 128 bits of I/O to
>the chip, each of which can be programmed in or out. Chips are usually
>tested by writing a C program that drives and senses the chip signals
>and most designers find this preferable to generating test vectors.
>Using this method, the tester runs at most at about .2 Mhz which is OK for
>functional testing. To do performance testing, a Tektronix DAS can be
>tied in and called as a subroutine to produce test vectors at up to 25 Mhz.
>Unfortunately, our DAS can only generate 15 bit vectors with the
>remainder being held static by the 68000. In spite of this, we have had
>little problem doing performance testing as it is fairly easy to
>identify a small set of bits can be used to do perfomance testing.
>From: Robert Montay <MONTAY@COLUMBIA-20.ARPA>
>
>We use a DAS 9100 logic analyser with tektronix software that allows a vax
>to be a host. Figure $25K, unless you can swing a donation.
>From: John Goodhue <goodhue@bbn-vax>
>
>In the "fancy machine" domain, we have recently been dealing with a
>company called LSI Testing inc. in Salem Mass (617) 745-2450. They
>provide engineering resources for test program development as well
>as time on their machines (Fairchild Sentry series) on a contract
>basis. I believe that they have a sister company on the west coast
>as well, but I do not recall their name. I think you will find that
>there are many places that can do functional and/or at speed testing
>for you on a contract basis, and quite a few software houses that
>specialize in the development of test software. Test software is
>(unfortunately) not cheap. We have been quoted $8750 for a chip
>that is only moderately complex (64 signal lines, approx. 300
>vectors for good coverage).
>From: gvax.kevin@Cornell.ARPA (Kevin Karplus)
>
>we have a somewhat slower tester based on an IBM PC with a digital
>oscilliscope board. I think we have only 32 I/O pins (input or ouput in sets
>of 8). It is very cheap, especially as the PCs are used in the Junior EE lab,
>so no new machines were needed. Software was written to download esim files
>to the PCs over a serial line, where they can be used as test vectors. There
>were also some FORTH testing programs written, but I have no copies of them.
>From: Ted Sabety <TED@COLUMBIA-20.ARPA>
>
>We at Columbia uase a TEktronix DAS with networking software to a VAX
>running UNIX as a test system. We arepretty stisfied with it.
>Cost: between $12000 and 25000 depending on how much you need.
>From: Vernon L. Chi <chi%unc.csnet@csnet-relay.arpa>
>
>On the academic scene, we are aware of the following activity:
>
>The Stanford MEDIUM Tester - Rob Mathews, Irene Watson, Dave Chenevert
>of Stanford (DARPA contracts (MDA 903-79-C-0335, MDA 903-79-C-0680,
>and MDA-903-80-C-0432) ... which more or less directly executes the
>pin-ops constituting the SIFT test language (see MOSIS documents)
>I hear Mathews and Watson are no longer at Stanford.
>
>The MISE (Machine for In-System Evaluation of Custom VLSI Chips) -
>R. Bisani, M.J. Foster, H.T. Kung, K. Oflazer of CMU (CMU-CS-82-132)
>which I'm not sure is "real", even yet.
>
>A Functional Tester Design for the University Environment -
>Mark Sherred of MIT (gone to Amdahl), EE&CS VLSI Memo No. 82-111,
>which I'm not sure is "real" either.
>
>The Terak Tester - V. Chi of UNC. This is a tester in the class of
>the Stanford MEDIUM Tester; it's less efficient for chips with low
>pin counts, but better for higher pin counts. This is "real" - we
>have been using it for over two years to develop and verify logical
>correctness of numerous projects.
>
>We have a Stanford MEDIUM Tester here. After determining the cost of DMA
>interfacing (which brings its performance into line with our Terak Tester),
>we have decided not to use it.
>
>The price of the Terak and an Andromeda interface card is about the same as
>the hardware cost of interfacing the MEDIUM tester. The custom modifications
>to the Andromeda card are trivial (1/2 day of technician time), and a test
>head with ZIF socket will take another technician-day.
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