info-vlsi@ucbvax.ARPA (05/02/85)
From: The MOSIS System <VLSI@USC-ISIF.ARPA>
CMOS/VLSI TEACHER'S COURSE
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WHAT: A CMOS/VLSI COURSE FOR UNIVERSITY INSTRUCTORS
WHEN: JULY 22 THROUGH AUGUST 1, 1985
WHERE: MARINA DEL REY, CALIFORNIA
PARTICIPATION:
Participation is limited to U.S. University staff interested in teaching CMOS
design. Enrollment is limited to one representative per University.
Attendance is limited to 45 students. A waiting list will be kept.
The course is free; however, participants are expected to cover their own
traveling and living expenses.
INSTRUCTORS:
Prof. Charles L. Seitz, California Institute of Technology
Prof. Mark A. Horowitz, Stanford University
Dr. George W. Lewicki, USC Information Sciences Institute
COURSE DESCRIPTION:
The principal goal is to provide prospective teachers with the technical
background, course material, logistical knowledge, and design experience
required to offer up-to-date VLSI design courses. The course will run for two
weeks (10 very long working days), and will include lectures, seminars, and a
project. The projects will be designed in MOSIS scalable CMOS/Bulk technology
using SUN workstations and the UC Berkeley "Magic" CAD programs.
The "academic core" material will be presented by Professors Seitz and
Horowitz, and will be supplemented by extensive notes on CMOS design. These
lectures are intended to (a) cover the material and (b) suggest how it can be
presented to students. Material critical to getting started on projects is
covered in the first week; more advanced material is covered in the second.
Primarily during week two, guest lecturers will discuss specialized and
advanced topics in coordination with the course outline, including:
- CAD tools
- Course logistics
- Circuit design
- Processes
- MOSIS services
The design projects are intended to be of a scale and character comparable to
those done by students in a one-quarter or one-semester first course in VLSI,
but can be more ambitious for students who come with fully developed project
ideas and plans. The course instructors will review all projects daily, and
ISI will provide wizards to help in the use of CAD systems. All students will
be expected to give brief oral reports on their project development during the
last day of the course.
COURSE OUTLINE:
1. An Informal Introduction to VLSI
Very Large Scale Integration -- Levels of abstraction -- Design disciplines and
rules -- scaling
2. Switching Model of MOS Systems
MOS transistors and wires -- Switching model -- Switch networks -- Switching
Algebra (review) -- Making voltages from switches in complementary logic --
Precharge techniques -- Switch Simulation I
3. Combinational Design
Programmed logic arrays (PLAs) -- Simplification of switching expressions
(review) -- Weinburger arrays and other regular layout schemes -- Function
blocks and decoders -- The symmetric network -- Combinational shifters --
Iterative arrays and arithmetic
4. Sequential Systems
Storage elements and timing -- Finite-state machines -- The paradigm of
datapath and control -- Best laid plans -- Switch Simulation II
5. Layout Disciplines
Floorplanning -- Composition tools -- Cell layout -- Cell layout tools --
Geometry verification
6. Electrical Engineering of MOS Systems
The CMOS/Bulk process -- Basic device equations -- Circuit Simulation --
Process parameters -- The tau model -- Delays in pass networks and wires --
Ratios in CMOS and nMOS -- Power and noise immunity considerations
7. Design for Performance
The tau model applied to systems -- Timing verification -- Bootstrap circuits
-- Analog digital circuits
8. Interacting with MOSIS
Description of MOSIS -- How to query MOSIS -- How to submit designs
ENROLLMENT:
Please forward all inquiries by letter to:
Kathleen Fry
The MOSIS Project
USC Information Sciences Institute
4676 Admiralty Way
Marina Del Rey, CA 90292-6695
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