G.DYER@SU-SCORE.ARPA (Landon Dyer) (02/03/86)
I sent a bogus description of the ST's bus cycle architechure to this list. I apologize. This morning I collared one of the hardware people here and shook the real description out of him: There are two 250ns windows. One window is for "static" system requests (video DMA and memory refresh). The other window is available for disk DMA, blitter DMA, and processor accesses. Refresh cycles are done during horizontal and vertical blank (and take, say, 5% of the first window). When the first window is not being used, it is available to fill requests that would otherwise go to the second window. I don't know exactly how much bandwidth is used by memory refresh cycles, but it is low. 5% is probably not too far off. Please forget my earlier misdescription of the bus architecure .... -landon -------