hull@hao.UUCP (Howard Hull) (11/23/83)
Since there is no "net.msi" - From COMPUTER DESIGN Magazine (A PennWell Publication) [without permission] November 1983, p.87 System Technology/INTEGRATED CIRCUITS: [Caveat: Not an advertisement - by either me or CD] Commercial GaAs digital IC's run at 2 GHz Digital integrated circuits using gallium arsenide technology will soon be released as commercial products by Harris Microwave Semiconductor. The first products will be small scale integration (SSI) parts using a 1-micron process on 2" (5-cm) wafers. They will include a 4-bit universal shift register and a divide by 2/4/8 divider. Clock speeds will initially be 1.5 to 2 GHz. These initial parts are primarily intended for signal processing applications which push the digital front closer to the raw signal, taking over functions that were formerly performed by analog devices. Harris' interest in digital GaAs IC's however, appears to be long term and is turning toward the computer arena. A joint contract is currently underway between Harris and Cray Research (Mendota Heights, Minn) for exploration of memory and gate array technology. The goal of this joint venture is to develop a 64- x 1-bit RAM chip. Since memory technology generally drives gate array technology, first developments from this project are expected to be GaAs memory chips. To achieve emitter- coupled logic (ECL) compatibility among the chips, the reference voltage to a given value is set depending on whether the device is operating in a GaAs environment or interfacing to ECL. The soon to be released 1.5-GHz shift register utilizes a serial or parallel I/O, shift right or left, and has a setup time of less than 350 ps. The chip is approximately 80 mils per side, and is housed in a flatpack. Numerous ground pins are interspersed among the signal pins to reduce crosstalk at high clock speeds. Power dissipation for the shift register is currently about 1.5W. In addition to the divider and shift register, Harris plans to introduce various SSI logic elements, such as flipflops, NAND, NOR and XOR gates, and buffers, within the next six to nine months. Clock rates for these parts are anticipated to be in the 3- to 4-GHz range. Harris is revamping all aspects of the technology - from designing and building its own large capacity crystal grower to creating its own test equipment - and foresees the technology evolving along a learning curve that will significantly reduce power dissipation and increase speed. Current power dissipation is approximately 40 mW per gate, and 0.5 mW per gate is considered feasible. Although low power is not a primary objective at this time, it will become a significant concern as circuit complexity increases. Among the current advantages are the wide operating temperature range, -55 to 100 degrees C and a substantially greater hardness to radiation than silicon. In addition to the ICs to be released, Harris considers currently feasible a gate count complexity up to 200, and a typical power dissipation of 15- to 25- mW gates. Custom IC engineering and device fabrication is available now, and Harris is presently moving to 3" (8-cm) wafers. Four different devices are already fabricated on a wafer and the larger size will undoubtedly increase yield and reduce costs. Harris Microwave Semiconductor, 1530 McCarthy Blvd, Milpitas, CA 95035.