geoff (12/21/82)
A friend is building a bit-slice engine with multiple processors. At the conventional machine level, they will appear as a single processor with multiple, pipelined ALUs. I've been invited to write a compiler for a restricted class of arithmetic expressions (no functions), so I'm looking for references to the literature. The ALUs are actually special-purpose; the compiler will be take as parameters the number of adders, multipliers, etc. If two adds are performed in succession, they will go to different adders if there are enough free adders, and the conventional machine level does this invisibly. The only similar machines that I know of are the CDC 6400 series (including Cybers) and the IBM 360/91. I'm looking at Computer Engineering by Bell, Mudge and McNamara. Any other pointers would be *much* appreciated, as this is being done in a hurry.