[net.arch] Cray vs ICs

henry@utzoo.UUCP (Henry Spencer) (06/11/83)

I seem to recall reading that there were more subtle reasons than
sheer suspicion of non-custom ICs for the relative lack of MSI and
LSI in the Cray-1 and its relatives.  There is some sort of problem
with getting proper line terminations on connections within ICs,
and line terminations were something that needed enormous amounts of
attention in the design of the Cray-1.  Hence (with the exception
of the RAMs) the chips in the Cray machines have, so to speak, no
internal connections at all -- they are simple NAND gates.

peachey@hssg40.UUCP (06/15/83)

	A reason for the lack of MSI/LSI in the Cray-1:

	Apparently, the Cray-1 is implemented with ECL (emitter-coupled
	logic).  Switching noise is generated when an ECL gate changes
	from driving a load to not driving a load.  However, since most
	ECL gates have both normal and inverted outputs, it is
	possible to virtually eliminate switching noise by terminating
	an equal number of inverted and normal gate outputs.  This
	ensures that as many outputs are changing to logic 1 as are
	changing to logic 0, which avoids generating power supply spikes.
	This "balancing" technique was apparently used on the Cray-1.  It
	can be difficult to do this with "off-the-shelf" MSI and LSI
	components, since some gate outputs within the chip are likely to be
	unbalanced.

					Darwyn Peachey
					utah-cs!sask!hssg40!peachey
					utcsrgv!sask!hssg40!peachey

rmiller@ccvaxa.UUCP (06/18/83)

#R:utzoo:-301300:ccvaxa:4700001:000:288
ccvaxa!rmiller    Jun 16 19:29:00 1983

cray also had trouble getting any custom ic's that would stay together
under the clock time that he wanted. the chips kept losing leads. but it
is rather interesting that there are only 4 types of chips in the cray-1
(a couple of NAND type chips, a shift register, and the memory chips).

emma@uw-june.UUCP (06/23/83)

What's this I hear about Seymour giving up on the Cray 2?  A CDC rep
mentioned it to me yesterday... apparently it was in the Minneapolis
Herald?

-Joe P.

hal@cornell.UUCP (06/24/83)

I recommend the article "The CRAY-1 Computer System" by Richard M. Russell
of Cray Research (CACM vol. 21, no. 1, pp. 63-72, 1978), which explains,
among other things, the reasons for the very simple chip types in the machine.
(The four chip types are 16x4 bipolar register chips [6 ns. cycle], 1024x1
bipolar memory chips (50 ns), and two types of bipolar logic chips.)  A 
paragraph near the end of the article is worth quoting:

"CRAY-1 modules are 6 inches wide.  The distance across the board is about
a nanosecond which is just about the edge time of the electrical signals.
Unless due precautions are taken, when electrical signals run around a board,
standing waves can be induced in the ground plane.  Part of the solution is to
make all signal paths in the machine the same length.  This is done by padding
out paths with foil runs and integrated circuit packages.  All told, between
10 and 20 per cent of the IC packages in the machine are there simply to pad
out a signal line.  The other part of the solution was to use only simple gates
and make sure that both sides of every gate are always terminated.  This means
that there is no dynamic component presented to the power supply.  This is the
principal reason why simple gates are used in the CRAY-1.  If a more complex
integrated circuit package is used, it is impossible to terminate both sides
of every gate.  So all of the CRAY-1's circuits are prefectly balanced.  Five
layer boards have one ground layer, two voltage layers, and then the two logic
layers on the outside.  Twisted pairs which interconnect the modules are
balanced and there are equal and opposite signals on both sides of the pairs.
The final result is that there is just a purely resistive load to the power
supply!"

(Copyright (C) 1977, ACM, copied by permission)


Folks who design supercomputers have strange and wonderous things to worry
about.


Hal Perkins                         uucp:  {decvax|vax135|...}!cornell!hal
Cornell Computer Science            arpa:  hal@cornell
                                  bitnet:  hal@crnlcs

rh@mit-eddi.UUCP (Randy Haskins) (06/24/83)

I'm convinced that Cray has a 'Z' missing in his name.
Of course, he can get away with it.  This is the kind
of stuff that we all should be doing, except that it's
easier to use models, so we have to be more careful 
about keeping things within the LIMITS of the model.
(I capitalize LIMITS because it's what makes models
bad.)  Anyway, I've been reading net.flame too much.
Sorry.
				Randy
				rh@Mit-eddie

vtl@stolaf.UUCP (06/29/83)

Yes, it is true.  An article in the Minneapolis Tribune (not Herald, sorry)
quoted him as saying that since the Cray 1 had been sped up--a recent
development by an independent design team--that the Cray 2 wouldn't be
fast enough.

Looks like it's back to the drawing boards.  If people are interested,
I can probably be talked into typing in the good parts (eg. no company
history, odd trivia, etc).  On the other hand, Cray Research will probably
be joining the net in the next few months, so maybe we can get some of this
information second (instead of fourth or fifth) hand.

Victor Lee -- St. Olaf College, Northfield MN -- ihnp4!stolaf!vtl

cytron@uiuccsb.UUCP (07/02/83)

#R:stolaf:-106700:uiuccsb:5600001:000:412
uiuccsb!cytron    Jul  1 11:05:00 1983

That's very interesting.  My understanding was that the speedup of the
Cray-1 (I think it is dubbed XMP) was due to a relaxing of the machine's
synchronous operation coupled with a higher yield of chips that operate
in the 8 ns. range.

I had thought that the Cray-2 was to be an improved *architecture* over
the Cray-1.  Is Cray telling why their new architecture could not out-
perform the souped-up Cray-XMP?

sys@stolaf.UUCP (07/05/83)

It looks like I need to clarify my last posting regarding the Cray-2.
It is true that the original Cray-2 was canned.  Since it never went into
production, its replacement will also be called the Cray-2 (how clever).
Perhaps a quote from the article (6/12/83 Minneapolis Tribune) will help...

	"In the fall of 1982 it was obvious that the Steve Chen (a Cray
	development vice president) group had done an excellent job on the
	Cray-1 enhancements.  They were close enough so that the original
	Cray-2 goals were not aggressive enough to warrant continuing,"
	Cray said.

	So Cray began a major overhaul of his Cray-2 design.  Because the
	enhanced Cray-1 was offering two to five times the speed of the
	original Cray-1, his first Cray-2 wouldn't be a significant
	improvement if it offered only six to 12 times the Cray-1's original
	speed, he reasoned.

	But Cray is nothing if not a poet in the world of complex equations
	and high-technology design tradeoffs.  He wove a new kind of meter
	and rhyme that the world has not seen before: Eight computer processors
	working together at 48 times the speed of the original Cray-1.

	Naturally, it hasn't been cheap.  Cray Research has had to build
	an integrated circuit factory in Chippewa Falls [Wisconsin] to make
	high-speed computer chips out of a new material called gallium
	arsenide.  In upgrading the Cray-2 memory, it scrapped $3.6 million
	in old memory components--writing off more than a quarter of the
	1982 Cray-2 research-and-development budget.

	That high-speed model using gallium arsenide chips won't be available
	until 1986, although a slower version using conventional silicon
	chips will be sold next year.  Both are likely to sell for more than
	$10 million each.

	The success of this improved Cray-2 design pleases Cray immensely.
	"I was not an outstanding contributor (to Cray Research) last year,"
	he said.  "But I hope to be this year."

		.
		.
		.

Sorry about the confusion,
Victor Lee -- St. Olaf College, Northfield MN -- ihnp4!stolaf!vtl

tom@rlgvax.UUCP (07/07/83)

with reports that the Cray 2 will not come out, what will happen to
the UNIX System V they announced will come out on the Cray 2?

- Tom Beres
{seismo, allegra, brl-bmd, mcnc}!rlgvax!tom