[net.arch] loop registers?

ucbesvax.turner@ucbcad.UUCP (07/12/83)

#N:ucbesvax:12800005:000:781
ucbesvax!turner    Jul 11 19:06:00 1983

	Does anyone out there know of a processor with a "loop branch
point" register--i.e., a register which holds a pc-value for continuation
of loops?  To give a simple example of string copy:

	...			! a0,a1 with char pointers:
	lea	bpr, pc		! next instruction loc -> loop branch point
	movb	@a0+, @a1+ 	! copy byte, post-incrementing
	loopnz			! pc <- lpb if byte was nonzero
	...

	Of course, I suppose you could just say "jnz a2" instead,
using a2 as a branch-point-register, if you really wanted to get into
tricky code optimizations.  It seems preferable to garbaging up the
architecture with special registers and instructions.

	As an alternative question, then: does anyone know of code
generators which do such optimizations?

	    Michael Turner
	    ucbvax!ucbesvax.turner