kester@houxq.UUCP (08/14/83)
Synapse Computer Corporation is sponsoring a seminar on their SYNAPSE N+1 (*TM) machine architecture. The machine has a multi-processor and a shared memory architecture. The system is modularly growable, provides load balancing and some fault tolerance. The seminar will discuss the architecture of their bus structure, (64 megabits aggregate throughput), the caching algorithm between shared memory and the General Purpose Processor (Each GPP has 16 Kbyte worth of cache). The design of the GPP will also be discussed. The date is Modany Aug 15 at 10 a.m. The place is Synapse Corp. #19 West 44 th street suite 316 N.Y. city Please call Ronnie Whitson at 212-391-1966 if you wish to attend the meeting. If you cannot reach her, just show up and introduce yourself, the meeting invitation is open.