[net.arch] RISC vs. 432

tdl (11/23/82)

Has anyone else seen the 11/17 issue of Electronics
magazine? There is an article on RISC (and Patterson didn't
even write it!). The interesting part is the companion
article with quotes from Rattner about the 432.  He says
that the 432 is really not that different from the RISC.
Who is he trying to kid? I can't believe he feels that he
has to defend his design like that. The two approaches are different;
period.  If he wants to defend his design he should point out
its advantages.
    He also says that the 432 is vertically microcoded,
"like RISC", and that most instructions execute in a single CPU
cycle. One, I can't believe that RISC is vertically microcoded, and two,
I can't believe that any of the 432's instructions execute in one cycle.
(Well, maybe NOPs)
    Any comments or facts?
				Tom Lovett
				Bell Labs at Freehold, NJ
				houxh!tdl

gnu@sun.UUCP (John Gilmore) (11/30/83)

The guy who said "Where is memory management?  Finish the job!" about
the RISC should look again at the 432.  It won't even talk to standard
memory chips without a special "packet bus controller" chip.
Personally I'd rather build an MMU from standard parts than I would a
packet bus controller.  Our 68010 MMU runs 400ns cycles, drives standard
64K rams, and doesn't add any wait states.

The RISC takes a trap when its register stack gets close to full.
The trap handler saves 1/2 the stack or so in memory and resumes the
user program.  There is some tuning that can be done in the stack
management software to minimize the number of "page faults" here;
one of Patterson's papers explains in more detail.  Remember that the
registers on chip are designed to be a cache.  Stack faults occur when
the hit rate drops below 100%.

Calling a subroutine to multiply doesn't cause stack overflows, since
it returns before it calls anything else.  Only deeply nested procedure
calls cause stack faults.