[net.arch] risc registers versus cache memory

muller@sdccsu3.UUCP (12/01/83)

You can view both risc registers and cache memory as a way of reducing
memory access bottlenecks. Cache memory increases speed by reducing the
number of accesses to slower main memory. However a properly designed
risc machine and compiler can have the same effect. The large number
of registers can be used in the same manner as a cache memory. If the
compiler can generate code such that a large percentage of the operands
are in registers the number of main memory accesses are reduced.

Keith Muller
UCSD CS Dept