zben@umcp-cs.UUCP (12/08/83)
. <-- Nigel to the rescue Through the magic of modern (?) electronics the Univac registers appear in the memory locations 0-0177, but there are some caveats to be considered. You may *not* put instructions into the registers and jump to them. You may *not* attempt to do partial word operations to the registers. This is why: The diversion of memory references <0200 does *not* occur for the P register fetch path. It is possible to construct a program in which core addresses 0-0777 are actually there, in this case instructions come from the (so called "shadow") core, but data references the registers. There are even more arcane results with the SLJ instruction, but if I were to describe them this article would become much too long.... :-) Partial word masking and stuffing are done in the memory interface unit. This is *after* the diversion. Thus if you attempt to do a partial word operation to a register, the partial word designator is ignored and a full- word transfer always takes place. TI's choice of putting the registers in core is sort of interesting. The stated reason was to speed up context-switching, since only the three registers actually on-chip (P counter, workspace pointer, processor status) need be saved and restored. However, this means many more buss cycles, for any instruction that references a register must initiate a buss cycle. Thus in speeding up context switching they *greatly* slowed down everything else! On the other hand, they used the chip real-estate freed up by not having real registers to implement hardware multiply and divide. However, it is an undocumented feature of the TI 9900 that you can put an instruction into the registers AND JUMP TO IT. I have used this feature by putting a return instruction into the register, SUBROUTINE JUMPING TO THE REGISTER (which immediately returns), then using the P counter address developed to implement position independant code. All I can say is: "caveat programmer"... I believe the low-end IBM 360 (/20 and below?) processors actually did have the registers implemented in low core storage. Ben Cranston ...seismo!umcp-cs!zben zben@umd2.ARPA