smith@umn-cs.UUCP (Richard Smith) (12/09/83)
#R:fortune:-190000:umn-cs:13900005:000:740 umn-cs!smith Dec 8 12:16:00 1983 True, in typical machines you can never use as much memory for general registers as you can for cache memory. BUT, the argument about addressability does NOT apply to RISC machines. From what I understand, the RISC instruction set is able to address some modest number of registers. This modest number is far smaller than the actual number of registers on the RISC chip. The registers you really use at any particular time are selected by a window setting. The window is shifted when a subroutine call or return takes place. There is still a serious difference here between pure cache and registers as described here -- we still aren't cacheing our instruction fetches. Rick. [smith.umn-cs@CSNet-Relay] [...ihnp4!umn-cs!smith]