[net.arch] Risc registers vs. cache

sdaniels@tymix.UUCP (Scott Daniels) (12/13/83)

[Please don't kill my text]

	I worked for a short while on a project to do microcode for a DEC-10 
look-alike (ie a machine with registers in the same address space as normal
memory).  Although we even included special hardware support to cope with 
separating the register and memory accesses, the problems of coping with 
onboard data (registers) and memory data caused innumerable headaches, and
in many cases slowed down the final implementation.  Some of the more obvious
problems:
    1) If you pipeline instructions, you better be able to invalidate
	the pipe if one of the cells with those instructions changes.
	This may include the results of register only operations if the
	program counter is allowed to wander into the registers.  The general
	rule from this seemed to be: registers should not overlap instruction
	-space.
    2) If the operands and the result do not overlap, restarting an instruction
	is much easier.  In some cases an instruction must not be allowed to
	go to completion (memory errors as well as interrupts).  To accomplish
	this, some of the instructions set up an "undo instruction" area, and
	the undo occurs in order to allow retries or continuation to happen.
	This setup takes time (or a lot more hardware).  When registers and
	data space are separated, load and store operations are nicely aranged,
	and you can often set up arithmetic so that you only hit on the reg
	after you know you will run to completion.
  
  -Scott Daniels (... ucbvax!hplabs!oliveb!tymix!sdaniels)