crandell@ut-sally.UUCP (Jim Crandell) (12/08/83)
> How about that ? Seymour Cray was right !!! :-)
I seriously doubt that anyone who has written a compiler for a CDC 6x00
ever imagined otherwise. If you haven't tried it, you should. Take
FORTRAN (please) or any other language whose inherent operations and
types map well onto the machine's instruction repertoire and internal
representations, and assume that you have expression trees of the
customary sort to work with. You can EASILY write a code generator
whose output is on an efficiency par with, say, MNF.
If the result of the foregoing exercise doesn't impress you, then
work the same problem again, substituting "Z-80" for "CDC 6x00".
Try it. You'll like it.
--
Jim ({ihnp4,kpno,ut-ngp}!ut-sally!crandell or crandell@ut-sally.UUCP)paulh@tektronix.UUCP (Paul Hoefling) (12/13/83)
>> Newsgroups: net.arch >> Subject: Re: risc registers versus cache memory >> >> You can view both risc registers and cache memory as a way of reducing >> memory access bottlenecks. Cache memory increases speed by reducing the >> number of accesses to slower main memory. However a properly designed >> risc machine and compiler can have the same effect. >>> The large number >> of registers can be used in the same manner as a cache memory. If the >> compiler can generate code such that a large percentage of the operands >> are in registers the number of main memory accesses are reduced. <<< >> >> Keith Muller >> UCSD CS Dept >> How about that ? Seymour Cray was right !!! :-) Happy computing... Paul Hoefling (...!teklabs!tektronix!paulh - usenet) (paulh at tektronix - csnet) (AB00PLH on Cyber)
faunt@hplabsc.UUCP (Doug Faunt) (12/15/83)
KA-10 (PDP-10) registers were in memory, unless you got an option.