szs@inmet.UUCP (12/10/83)
#N:inmet:2500007:000:1842 inmet!szs Dec 1 16:54:00 1983 I'm trying to do an evaluation of ISA technology to find ISAs which will support Ada, for the next generation of Navy processors. This discussion group has thus been a source of great interest to me. There seem to be three basic choices in the field now: ISAs with great complexity (Nebula, iAPX432), "run of the mill" ISAs (PDP-11, MIL-STD-1750A, AN/AYK-43,44, etc.), and RISCy things. There are ample results for Ada implementations for the middle category. Code generation is sometimes a pain in the butt but doable. Results are often less than satisfactory. I've first-hand experience with Ada 432, with much less than satisfactory performance. FIRST QUESTION: Is it the "memory management" access descriptor BS that slows it down or the complexity of the 432's ISA in general??? Nebula seems to have the same instruction complexity (approximately) as the 432, but with more "conventional" memory management. SECOND QUESTION: Does anybody know how well Nebula works?? It seems that writing an Ada code generator for Nebula will be a piece of cake (compared to, say, MIL-STD-1750). 3RD QUESTION: (for SofTechers) Is this true?? The dearth of real performance info for RISC is frustrating. Details in Radin's and Patterson's stuff are too sketchy. 4th Q: Does anyone have some size/time comparisons along with the RISC "assembly" code for some common algorithms?? (turner?? and what's this simulator you've got??) (Side comment: It seems that at least some of the remaining 94% of the computer design job has been thrown in the compiler writer's lap for RISC.) 5th Q: Given that Ada compilers are already almost too complicated to get right until the 4th or 5th try, is it wise to give the compiler writers the job of creating a meta-ISA also??? -Steve Stein (decvax!harpo!inmet.szs) p.s. hi gary at ncsu and jerry at yalecom
howard@metheus.UUCP (Howard A. Landman) (12/16/83)
In partial answer to Steve Stein (decvax!harpo!inmet.szs): FIRST QUESTION: Is it the "memory management" access descriptor BS that slows it down or the complexity of the 432's ISA in general??? I'm sure Intel has thought about this a lot. But have you looked at the article on the 432 by people at Berkeley (including some RISC-ers)? The full reference was published on the net a month or so ago. Look for an article by wateng!pparkinson. The dearth of real performance info for RISC is frustrating. Details in Radin's and Patterson's stuff are too sketchy. Why don't you ask some the people involved? I'm sure that Dave Patterson and Manolis Ketevenis, for example, would have data or references (or both) that you would find useful. Try ucbvax!pattrsn and ucbvax!kateveni; these used to be valid. And the commercial RISC-oids should be more than happy to deluge you with performance info (anyone at Pyramid Technology listening?). Does anyone have some size/time comparisons along with the RISC "assembly" code for some common algorithms?? The size comparisons were published long ago for RISC I. Again, have you read all the references in wateng!pparkinson's listing? The early time comparisons were of course estimated because the chip hadn't been built yet. More recent papers have more accurate info based on running the actual chip. The assembly code for many small programs (including all the cited benchmarks) either exists at Berkeley or can be easily recreated since it was produced by a compiler, although there were some small diagnostic programs that were hand-coded in assembler. (Side comment: It seems that at least some of the remaining 94% of the computer design job has been thrown in the compiler writer's lap for RISC.) Au contraire: writing compilers for machines with simple architectures is EASIER than writing similar compilers for machines with complex architectures, IF the architectures both provide adequate support for the HLL in question. A C compiler for the RISC I was running months before the chip was finished, and helped find several early bugs in the design. (Recall that the chip was designed in 5 months.) The only sense in which your comment is true is that library routines for floating point had to be coded. Howard A. Landman (one of the designers of the RISC I chip) ogcvax!metheus!howard