mason@utcsrgv.UUCP (Dave Mason) (03/07/84)
I think this really belongs in net.arch, so let's move it there (they're
a lonely bunch anyway).
But to the topic:
There are not any large Dual Ported Memories (DPMs) that I am aware of,
but there are some small DPMs that really are 2 accesses at once. The way
they work is (I believe) that there are 2 copies of every peice of data,
and whenever a change is made via one port, it is shadowed over to the other
at some (hopefully soon) convenient time. This way there can be no conflicts
on accessing...much better if you want a synchronous architecture.
Fairchild (probably among others) makes some of these chips..the largest I
know of being something like 32 words x 8 bits. They are intended as register
banks in a CPU, so the speed is probably within your requirements (about 20ns)!
--
{dalcs dciem garfield musocs qucis sask titan trigraph
ubc-vision utzoo watmath allegra cornell decvax decwrl ihnp4 uw-beaver}
!utcsrgv!mason Dave Mason, U. Toronto CSRG