[net.arch] IBM 801 Cache / Re: RISC perspective

phipps@fortune.UUCP (Clay Phipps) (03/13/84)

The IBM 801 experimental minicomputer has cache-controlling instructions,
for approximately the reasons stated elsewhere in this newsgroup.
Particularly compelling were the desire to avoid loading all of a cache line
(32 bytes) when a single word (4 bytes) was referenced in a newly-allocated
area, such as are used for routine stack frames and i-o buffers.
The cache of the 801 uses a "store in cache" rather than "store thru cache"
strategy.

The only material on the 801 that I've seen outside of IBM is

    George Radin: "The 801 Minicomputer",
    *Proc. of the Symposium on Architectural Support
    for Programming Languages and Operating Systems*
    (SigArch *Computer Architecture News*, vol. 10, num. 2, March 1982,
    or *SigPLan Notices*, vol. 17, num. 4, April 1982),
    p. 39 .. 47.

I wonder if that project is still active ...

-- Clay Phipps

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