wm@tekchips.UUCP (Wm Leler) (04/12/84)
In the just-out issue of Computer Architecture News (v12, #1, March 84) there are two articles about RISC architectures. The first one runs benchmarks the RISC I. They were trying to eliminate differences in performance caused by using different compilers, *and* they eliminated the register window scheme, and the RISC still performed as well as a 68000 or a Z8000. The second one is a report on the RISC II by David Patterson. Pretty slick. They have some benchmarks for a large program, and some estimates for other RISC architectures, including an ECL RISC implementation that would fit on one board. This paper "concludes with a short description of our next project," "Smalltalk on a RISC, or SOAR." They hope that "SOAR will show that a Reduced Instruction Set Computer can be a low cost, high performance Smalltalk machine." Wm Leler tekchips!wm