george@hhb.UUCP (05/10/84)
From the highly fragmentary blurbs available, the Cray-2 looks like it may be a disappointment for both vector and scalar processing. One of the weaknesses of the Cray-1 was that the CPU had only one port to memory. Among those problems amenable to vectorization, the limiting factor was usually memory bandwidth (with happy exceptions like matrix multiply), since a vector read tied up memory completely. The Cray-2 is said to be 6-12 times faster - now, with a cycle time 3 times faster and 4 processors, we've got the 12 taken care of. There is no hint that the above defect has been addressed. I find this very odd, because the dual processor Cray X-MP allows EACH processor to do 2 vector loads, a vector store, and I/O concurrently, allowing up to 5x speedup, according to Cray promotional literature ( I reckon 2x for the 2 processors, 2x for the added ports, and 1.3x for the cycle time, equals 5, in fact). But for the difference in cycle time, a 4-processor Cray-2 might be no faster than a 2-processor Cray X for most vector problems. It seems better on principle to have fewer fast processors than many slower ones. The other peculiar thing is the slow MOS memory they're using. EIGHT YEARS ago, Cray used 50 ns ECL RAM; now they're going to use 100 ns RAMs ??? True, for vector processing, it hardly matters (worse startup and a longer list of undesirable increments to avoid). Also true, there are no doubt lots of registers for do-it-yourself caching. Agreed, Cray and CDC found that equipping their older machines with MOS memories didn't hurt as much as feared (it didn't exactly help, though). Obviously too, MOS is denser and cheaper, which matters when you use a lot. On the other hand, if loading a register takes 4 times as long as a floating-point multiply, then something is wrong. This can hardly be the Seymour of old. After all, the original 7600 had half the memory of the original 6600, and nobody complained. I have a theory. Available 16K ECL RAMS have 15 ns access times, about what is needed to keep the CPU/memory speeds constant. However, they're made by Fujitsu. Seymour doesn't buy Japanese. And it's unacceptable to settle for second-best 35 ns chips just for patriotism. So, he went for the 256K chips, pretending that's what he wanted all along. Does anybody have details of any kind about the Cray-2 or the Japanese supercomputers? Did the Japanese just use leftover 370 opcodes for vector instructions or what? For that matter, what is the memory cycle time on the Cray X-MP? Information/insights would be appreciated. George Shrier HHB-Softron
sharma@uicsg.UUCP (05/16/84)
#R:hhb:-15200:uicsg:3200005:000:430 uicsg!sharma May 15 21:10:00 1984 Cray-XMP Memory Cycle Time: The Cray-XMP memory consists of 32 banks - organised as 4 lines with 8 banks each. The two CPUs each have three memory ports and one I/O port. These four ports are connected directly to the four lines. The memory access time is 4 cycles ( 4 times 9.5 nsec ) i.e. each bank can accpet a request every 4 cycles. Each line, however, accepts a request every cycle. UUCP : ihnp4!uiucdcs!uicsg!sharma