tihor@acf4.UUCP (05/20/84)
Register banking can improve instruction speed homeogenaity by speeding procedure calls, potentially a very expensive operation. (Viz the VAX-11/7xx CALLS/CALLG instruction, a wonder to behold but not exactly as fast as an ADD.)
jon@hhb.UUCP (John Sissler) (05/22/84)
To all involved in the Pyramid RISC discussion:
I was under the impression (naive perhaps) that one of the
primary goals of the RISC architecture was to provide an instruction set
whose members all roughly shared execution times. This allowed the
implementation of a cheap, multi-stage pipeline. A complex instruction set
carries with it the burden of vastly different execution times, not
exactly an advantage to the architect trying to control a multi-stage pipeline.
Remember, pipelining is the greatest idea since cache, one for the memory sub-
system, one for the processor!
What does register banking have to do with the basic concept of
homogeneous execution times?
As a last note, if you want raw I/O or processor speed, you
probably have to pay ($) for it. The pyramid is a fantastic, cost
effective machine, don't humble the poor thing with raw processor
benchmarks, the register banks don't quite hum in a compute bound-
looping C-function!
john - HHB-Softron ...
" the people who brought you the original 90x non-aligned 32-bit move!"
UUCP address: {decvax,allegra}!philabs!hhb!jon