[net.arch] 'another RISC' machine

stevel@haddock.UUCP (05/22/84)

#R:decwrl:-33200:haddock:9500015:000:532
haddock!stevel    May 21 12:54:00 1984

RISC "Reduced Instruction Set Computer". It says nothing about
register windowing/banking. The main thrust of RISC is get rid of
the microcode and the time consuming, long critical path control
circuits. Leaving all that silicon for faster parallel arithmetic
and cache circuits.

All this register garbage is yet another idea. One with merit but
not inherently RISCy.

And none of the mentioned compiler optimizations are
restricted to RISC architectures.

Steve Ludlum, decvax!yale-co!ima!stevel, {ucbvax|ihnp4}!cbosgd!ima!stevel