brownell@harvard.UUCP (Dave Brownell) (05/23/84)
I'm familiar with the basics of the RISC concept as distinct from
any specific architectural requirements: limited instruction set
allowing faster hardware.
However, some recent submissions have implied there are a few
architectural requirements like register banks. These would seem
to come from the original Berkeley RISC chips, about which I'm
uninformed.
I'm after some pointers to papers on RISC. (I have access to the
Harvard and MIT CS libraries.) Historical perspective would be
very nice, as would some overview of working machines. Just how
successful has RISC been so far? How 'bout applications, especially
to AI?
I hesitate to suggest -- a few knowledgable replies could probably
get posted here, the volume doesn't seem too high. Literature pointers
straight to me, please, I'll summarize to the net. (I expect redundant
literature pointers.)
Dave Brownell
{allegra,floyd,ihnp4,seismo}!harvard!brownell