gnu@sun.uucp (John Gilmore) (05/30/84)
It occurred to me a year or two ago that you could gain about 5% in system performance if you had a refresh controller chip that actually kept track of which rows needed refreshing (haven't been referenced for 2ms) and which didn't. Since in executing typical code you hit 90 or 100% of the rows, the 5% refresh overhead should drop to .5 or 0%. I'm not clear on an optimal algorithm for figuring out which rows to refresh while always hitting all of them within 2ms, but I'm sure you could do a LOT better than refreshing every row every chance. The chip would have to deal with memory banking or interleave but this could probably just be done with one chip per memory bank anyway. This idea also occurred independently to Jim Lockwood (of NCR, now Sun) but nobody has taken either of us seriously. Why not, isn't 5% worth it?
phil@amd70.UUCP (Phil Ngai) (06/01/84)
This is an attractive idea because the refresh overhead is real and
noticable. It is complicated by multiple banks of memory (the banks
which are not accessed are still eligible for refreshing). The idea
of using a refresh controller per bank sounds expensive in $ and board
space. Because of the large number of pins (18 address in, 9 address out,
plus control, power and ground) you're probably going to need a 40 pin DIP.
I am assuming you mean to put the entire DRAM control in one chip. If you
want to let another chip do your muxing then you'd need fewer pins. Maybe
even let the address pins be I/O and only need 9.
It is an interesting idea. Maybe a good project for someone
in a LSI design class, or a first CMOS gate array.
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Phil Ngai (408) 749-5286 {ucbvax,decwrl,ihnp4,allegra,intelca}!amd70!philscottt@tektronix.UUCP (06/01/84)
I also thought it would be a neat idea to minimize the refresh overhead by remembering which rows had been accessed in the last 2ms by the processor or DMA controller. A few years ago I built a 14 chip TTL implementation to prove out the idea. Then as a project in a VLSI design class I was taking I implemented it on a single MOS IC (about 6K transistors). It was designed to interface to an existing DRAM controller, like an 8203 or 8409. It all worked as expected, but my employer wasn't interested, so I haven't done anything with it for a long time. Scott Trappe tektronix!scottt