eugene@ames.UUCP (Eugene Miya) (11/05/84)
Recently, a paper in Computer [IEEE], Oct. 1984 mentioned the content of the
infamous LLNL "Livermore Loops." I have been aware of the content of these
benchmarks for about 6 or 7 years now. Basically, they were written to
test "cute" ideas on CDC 7600 class serial processors. [My favorite is the
many way cascading branch loop which is supposed to fool lookahead pipelines.]
These programs have several problems with future high speed processors:
they are written in FORTRAN, they cannot distinguish vector from scalar
machines, they cannot distinguish various levels of parallelism (fine grained
dataflow from say Denelcor or Cray task-level parallelism).
A friend doing dataflow research at LLNL and I are interested in writing a set
of test program generators (in somewhat of a `reasonably' language-independent
way) as a follow on to the Livermore loops. I choose not to post this to
language group because determining performance characteristics (not just speed)
is my major concern. The orientation is numerical. We want to be able to
detect architectural differences such as dataflow architectures from vector
architectures, and so on. If a machine has N CPUs, we want to be able to
detect overheads and fall offs. If you are interested in discussing the
issues [we don't want to write code without giving this good thought], write
or phone me.
--eugene miya
NASA Ames Res. Ctr.
{hplabs,ihnp4,dual,hao,vortex}!ames!aurora!eugene
emiya@ames-vmsb.ARPA
New phone prefix: (415)-694-6453 (5197 mesgs)eugene@ames.UUCP (Eugene Miya) (11/09/84)
I am aware that benchmarks in the past tended to give single numbers which
ignorant managers would go running off into the void to argue for some
stupid machine. The intent of my solicitation for others interested in
benchmarking is to come up with a set of tests (don't call them benchmarks
then) which would be able to distinguish architectural characteristics
of various architectures. Several of us want to be able to determine
the extent of pipelining (hardware), dataflow architectures, vector architectures,
and so on. I realize this is not an easy task, but I want to give it a try
and I have a couple of other researchers also willing.
--eugene miya
NASA Ames Res. Ctr.
{hplabs,ihnp4,dual,hao,vortex}!ames!aurora!eugene
emiya@ames-vmsb.ARPA