pdbain@wateng.UUCP (Peter Bain) (11/19/84)
chuck@dartvax.UUCP (Chuck Simmons) suggests:
Now suppose we had a cache that was much more under a programmer's control.
To be concrete, suppose we have a cache of say, 32 elements each containing
32 words. And suppose our processor has a load cache instruction with
syntax:
load cache <cache address> <memory address>
When this instruction was executed, the instruction execution processor
would quickly tell the cache processor to pick up some data from memory.
Now, while the cache processor is picking up the data, the instruction
processor continues executing instructions which are already in cache.
This is actually what you do with registers. In a RISC, you can think of the
register bank as a cache for the top of stack. I suspect, though, that
the hassle of figuring out your data usage, may not give you that much
performance improvement. I believe that once a cache fills, the hit rate
is about 90% for a well-designed system. If you REALLY want arrange your
own cache, you could "touch" (read or write) locations you want brought in,
forcing a cache miss and load.
-peter (bring back the IBM 650) bain
--
- peter bain
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