kjm@ut-ngp.UUCP (Ken Montgomery) (11/08/84)
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Is anyone out there going to be manufacturing production RISC chips
anytime soon? If so, how can I get more information about them?
--
"Shredder-of-hapless-smurfs"
Ken Montgomery
...!{ihnp4,seismo,ctvax}!ut-sally!ut-ngp!kjm [Usenet, when working]
kjm@ut-ngp.ARPA [for Arpanauts only]marcus@pyuxt.UUCP (M. G. Hand) (11/13/84)
Someone was asking about the manufacture of RISC chips and their availability. Inmos makes a risc type chip that they call a transputer - actually it uses an OCCAM instruction set. The name is IMS T424. Briefly, its a family of 16 and 32 bit processors, with a 50 nanosec cycle time, 26 megabyte/sec memory interface with 4k static ram on the chip (70 ns) plus dma interface, hardwired scheduler etc, etc. More details from "Electronics" 56(23) 15pp p109 I. Barron,P. C. Avill, et al, "Transputer does 5 or more mips even when not used in parallel" Electronics, 11/17/83 Marcus Hand
bcase@uiucdcs.UUCP (11/19/84)
> Someone was asking about the manufacture of RISC chips and their > availability. > > Inmos makes a risc type chip that they call a transputer - actually > it uses an OCCAM instruction set. The name is IMS T424. Uh, by every account I have heard so far, Inmos has not yet made one of these things. Are my sources wrong? I would love to hear that Inmos is shipping or sampling transputers. We've been waiting and waiting and waiting.... bcase
srm@nsc.UUCP (Richard Mateosian) (11/25/84)
> I would love to hear that > Inmos is shipping or sampling transputers. We've been waiting and > waiting and waiting.... My contact at Inmos is Pete Wilson 303/630-4256. Perhaps they're not on USENET. Pete has been with the Transputer project for its entire five-year life. He's a likeable, enthusiastic spokesperson who will give you the straight story. Last time I talked to him he said that they'd seen silicon but it wasn't sampleable. The official Inmos line, if I remember correctly, is that they will sample in first quarter 1985. -- Richard Mateosian {amd,decwrl,fortune,hplabs,ihnp4}!nsc!srm nsc!srm@decwrl.ARPA