baskett@decwrl.UUCP (Forest Baskett) (11/27/84)
Suppose your virtual address is 32 bits and addresses bytes. If your page size is 4K bytes, you have twelve low order bits to use to access the real address cache while you are running the high order 20 bits through the translation buffer. The real address tags and the data come out of the real address cache at the same time (roughly) as the real address comes out of the translation buffer (assuming you didn't miss in the translation buffer). Then you check to see if you got a hit in the cache by comparing the real address with one or more of the real address tags. If none of the tags match, you got a cache miss and you send the translated address off to main memory. For this example, if your cache is direct mapped, you get one tag and the cache can be up to 4K bytes in size. If your cache is two-way set associative, you get two tags and your cache can be up to 8K bytes. If your cache is 4-way set associative, it can be up to 16K bytes. If you want bigger caches with this simple approach, you have to increase either the page size or the degree of associativity in each set. This is not a new idea. IBM has been using it for many years in their 370 style machines. Since they don't believe they can increase the page size, some of those machines have very high degrees of set associativity. We used a similar idea in the design of the memory management system for the Sun workstation in order to get no-wait-state memory accesses. The low order virtual address bits were sent to the memory immediately to be used for RAS while the memory management unit translated the high order address bits to be used for CAS. The page size was a byproduct of the rest of the memory system design. Forest Baskett - Western Research Laboratory - Digital Equipment Corporation