brownell@harvard.UUCP (06/05/84)
Here are the results of the request I posted for RISC manifestos
a week or two ago. Many thanks to Peter Bain (wateng!pdbain),
Kevin Kissell (flairvax!kissell), and Hal Perkins (cornell!hal),
who provided the references.
Such is life that I've not been able to look many of these up,
but as you can see most of the sources should not be all that
hard to find. They total 24 references; there was only one
duplicate. I've left these in the form I received them, both to
simplify my life and to reduce any transcription errors.
Dave Brownell
{allegra,floyd,ihnp4,seismo}!harvard!sequoia!brownell
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%A D.A. Patterson
%A P. Garrison
%A M. Hill
%A D. Lioupis
%A C. Nyberg
%A T. Sippel
%A K. Van Dyke
%T Architecture of a VLSI Instruction Cache for a RISC
%J Int. Symp. on Computer Architecture
%D 1983
%P 108
%A J.A. Fisher
%T Very Long Instruction Word Architectures and the ELI 512
%J Int. Symp. on Computer Architecture
%D 1983
%P 140
%A G. Radin
%T The 801 Minicomputer
%J IBM J. Res. Dev.
%D 1983
%V 27
%N 3
%P 237
%T MOVE Architecture in Digital Computers
%A Daniel Tabak
%A G.J. Lipovski
%J IEEE Transactions on Computers
%V C-29
%N 2
%D February 1980
%P 180-189
%A C.H. Sequin
%A D.A. Patterson
%T Design and Implementation of RISC I
%P 276-298
%A J. Hennessy
%A N. Jouppi
%A F. Baskett
%A J. Gill
%T MIPS: A VLSI Processor Architecture
%D 1981
%B VLSI Systems and Computations
%E H.T. Kung
%E R. Sproull
%e G. Steele
%I Computer Science Press
%P 337-346
%A P. Schulthess
%A F. Vonaesch
%T OPA - A New Architecture for Pascal-Like Languages
%P 9
%J ACM Computer Architecture News
%V 10
%N 6
%D Dec. 1982
%A M.V. Wilkes
%T Keeping Jump Instructions out of the Pipeline of a RISC-Like Computer
%J Computer Architecture News
%I ACM
%V 11
%N 5
%D Dec. 1983
%P 5-7
%T Strategies for Managing the Register File in RISC
%A Y. Tamir
%A C.H. Sequin
%J IEEE Trans. on Computers
%D Nov. 1983
David A. Patterson, `` A RISCy APPROACH TO COMPUTER DESIGN''
Digest of papers, Spring COMPCON 82 pp. 8-14
IEEE Computer Society press
Patterson, D.A., and Ditzel, D.R., ``The Case for the Reduced
Instruction Set Computer,'' Computer Architecture News, Vol. 8, No. 6,
October 1980, pp. 25-33.
Clark, D.W. and Strecker, W.D., ``Comments on `The Case for the Reduced
Instruction Set Computer,''' Computer Architecture News, Vol. 8,
No. 6, October 1980, pp. 34-38.
Hennessy, J., Jouppi, N., Przybylski, S., Rowen, C., Gross, T.,
Baskett, F., and Gill, J., ``MIPS: A Microprocessor Architecture,''
Proceedings from the 15th Annual Workshop on Microprogramming,
November 1982, pp. 17-22.
... note: related paper above, in VLSI Systems and Computations
Radin, G., ``The 801 Minicomputer,'' Proceedings from the Symposium
on Architectural Support for Programming Languages and Operating
Systems, March 1982, pp. 39-47.
Patterson, D.A. and Sequin, C.H., ``RISC I: A Reduced Instruction Set
VLSI Computer,'' Proceedings from the Eighth Symposium on Computer
Architecture, May 1981, pp. 443-457.
Fitzpatrick, Foderaro, Katevenis, Landman, Patterson, Peek, Peshkess, Sequin,
Sherbourne, & Van Dyke, "A RISCy Approach to VLSI," VLSI Design 4th Qtr 1981
Hansen, Mayo, Linton, Murphy, & Patterson, "A Performance Evaluation of the
Intel iAPX432," Computer Architecture News, June 1982
bench marks the 432 on the same test programs used to test RISC
Foderaro, Van Dyke, & Patterson, "Running RISCs," VLSI Design, Sept/Oct 1982
Katevenis, M.G.H, Sherburne, R.W, Patterson, D.A., and Sequin,
C.H., ``The RISC II Micro-Architecture,'' Submitted to the VLSI 83
Conference, August 83, Norway.
Larus, J.R., ``A Comparison of Microcode, Assembly Code, and
High-Level Languages on the VAX-11 and RISC I,'' Computer Architecture
News, Vol. 10, No. 5, September 1982, pp. 10-15.
Patterson, D.A. and Piepho, R.S., ``RISC Assessment: A High-Level
Language Experiment,'' Proceedings from the Ninth Symposium
on Computer Architecture, April 1982, pp. 3-8.
Patterson, D.A. and Sequin, C.H., ``A VLSI RISC,'' IEEE Computer,
Vol. 15, No. 9, September 1982, pp. 8-21.
Foderaro, J.K., Van Dyke, K.S., and Patterson, D.A., ``Running RISCs,''
VLSI Design, September/October, 1982.
I suggest you read "Reduced Instruction Set Computer Architectures for VLSI"
by Manolis G. H. Katevenis. This is the Ph.D. thesis written by one of the
designers of the RISC I & II. It is a tech report UCB/CSD 83/141 from the
Computer Science Division (EECS), University of California, Berkeley, CA
94720. There is a nice summary of the RISC project, the rationale behind
it, and implementation details of the RISC II chip.padpowell@wateng.UUCP (PAD Powell) (12/04/84)
The following is a list of papers concerned with the RISC architecture. Please feel free to suggest additions/revisions. Patrick Powell and Peter Bain VLSI Research Group, U. Waterloo ----- Cut Here ----- : Run this shell script with "sh" not "csh" PATH=:/bin:/usr/bin:/usr/ucb export PATH all=FALSE if [ $1x = -ax ]; then all=TRUE fi /bin/echo 'Extracting header' sed 's/^X//' <<'//go.sysin dd *' >header X.\" format using (nroff/troff) -me macros X.ce X.sz +10 RISC Bibliography X.sz -10 X.pp The following is a list of papers dealing with the X.i "Reduced Instruction Set Computer architecture. A partial form of this bibliography has been distributed over the USENET, and has been updated by Patrick Powell and Peter Bain of the VLSI Research Group of the University of Waterloo This is the December 3, 1984 edition. //go.sysin dd * made=TRUE if [ $made = TRUE ]; then /bin/chmod 644 header /bin/echo -n ' '; /bin/ls -ld header fi /bin/echo 'Extracting RISC' sed 's/^X//' <<'//go.sysin dd *' >RISC %l proceedings-article %A M. Castran %A R. P. Organick %T u3L: An HLL-RISC Processor for Parallel Execution of FP-Language Programs %J Proc Ninth Annual Symp on Computer Architecture %P 239-247 %M April %K RISC %D 1982 %l journal-article %T Comments on 'The Case for the Reduced Instruction Set Computer' %A D. W. Clark %A W. D. Strecker %J Computer Architecture News %V 8 %M Oct %D 1980 %K risc reduced instruction set computer restricted architecture %l journal-article %A B. Clifford %T Fewer Instructions Speed Up VLSI %J Electronics %V 55 %N 23 %P 101-102 %M November %K RISC %D 1982 %l journal-article %A R. P. Colwell %A C. Y. Hitchcock III %A E. D. Jensen %T Peering through the RISC/CISC Fog: An Outline of Research %J Computer Architecture News %I ACM %V 11 %N 1 %D 1983 %M March %P 44-50 %K archons 432 object-oriented overlapped multiple register sets %X attempt to determine if RISCs faster than CISCs, and why %l journal-article %A P. J. Denning %T Computer Architecture: Some Old Ideas that Haven't Quite Made It Yet %J CACM %V 24 %N 9 %P 553-554 %M September %K RISC %D 1981 %l journal-article %A Electronics %T Altering Computer Architecture is a Way to Raise Throughput Suggests IBM Researchers %J Electronics %V 49 %N 25 %P 30-31 %M December 23 %K RISC %D 1976 %l proceedings-article %A J. A. Fisher %T Very Long Instruction Word Architectures and the ELI 512 %J Int. Symp. on Computer Architecture %D 1983 %P 140 %K parallel data flow trace scheduling cray-1 RISC multiprocessor %l journal-article %A D. T. Fitzpatrick %A J. K. Foderaro %A M. G. H. Katevenis %A H. A. Landman %A D. A. Patterson %A J. B. Peek %A Z. Peshkess %A C. H. Sequin %A R. W. Sherbourne %A K. S. Van Dyke %T A RISCy Approach to VLSI %J VLSI Design %N 4th Quarter %D 1981 %K risc reduced instruction set computer architecture restricted %l journal-article %A J. K. Foderaro %A K. S. Van Dyke %A D. A. Patterson %T Running RISCs %J VLSI Design %N September/October %D 1982 %K risc reduced instruction set computer architecture restricted %l proceedings-article %A Thomas Gross %A John Hennessy %A Norman Jouppi %A Steven Przybylski %A Christopher Rowen %A Anant Agarwal %A Peter Steenskiste %T A Perspective on High-Level Language Architecture (extended abstract) %J International Workshop on High-Level Computer Architecture %I Univ. of Maryland %M May %D 1984 %K risc reduced instruction set computer restricted architecture %l journal-article %A Hansen %A Mayo %A Linton %A Murphy %A Patterson %T A Performance Evaluation of the Intel iAPX432 %J Computer Architecture News %M June %D 1982 %K risc reduced instruction set computer architecture restricted %X bench marks the 432 on the same test programs used to test RISC %l journal-article %A J. L. Heath %T Re-Evaluation of RISC 1 %J Computer Architecture News %D 1984 %M March %P 3-10 %V 12 %N 1 %K reduced instruction set computer benchmarks 68000 16000 %X comparison of performance %l manuscript %T Hardware/Software Tradeoffs for Increased Performance %A J. Hennessy %A N. Jouppi %A F. Baskett %A T. Gross %A J. Gill %O unknown publication %K risc reduced instruction set computer restricted architecture %l book-article %A J. Hennessy %A N. Jouppi %A F. Baskett %A J. Gill %T MIPS: A VLSI Processor Architecture %D 1981 %B VLSI Systems and Computations %E H. T. Kung %E R. Sproull %e G. Steele %I Computer Science Press %P 337-346 %K pipelines delayed branch jump reduced instruction set computer risc %l proceedings-article %A J. Hennessy %A et al %T MIPS: A VLSI Processor Architecture %J Proc of the CMU Conference on VLSI systems And Computations %P 337-346 %M October %K RISC %D 1981 %l proceedings-article %A J. Hennessy %A et al %T The MIPS Machine %J Proceedings of COMPCON Spring 82 %P 2-7 %M February %K RISC %D 1982 %l proceedings-article %A J. Hennessy %A N. Jouppi %A S. Przybylski %A C. Rowen %A T. Gross %A F. Baskett %A J. Gill %T MIPS: A Microprocessor Architecture %J 15th Ann. Workshop on Microprogramming %M November %D 1982 %P 17-22 %K risc reduced instruction set computer architecture restricted %l proceedings-article %A J. Hennessy %A N. Jouppi %A S. Przybylski %A C. Rowen %A T. Gross %T Performance Issues in VLSI Processor Design %J Proc. Intl. Conf. on Computer Design (ICCD) %D 1983 %P 153-156 %K mips risc reduced restricted instruction set computer architecture %K pipelining microcoding %l proceedings-article %A Martin E. Hopkins %T A Definition of RISC %J International Workshop on High-Level Computer Architecture %I Univ. of Maryland %M May %D 1984 %P 8-11 %K risc reduced instruction set computer restricted architecture %X Tries to definite RISCs in the IBM 801 context in comparison to the IBM 370 %l journal-article %A M. G. H Katevenis %A R. W Sherburne %A D. A. Patterson %A C. H. Sequin %T The RISC II Micro-Architecture %J VLSI 83 %M August %D 1983 %K risc reduced instruction set computer architecture restricted %l dissertation %T Reduced Instruction Set Computer Architectures for VLSI %A M. G. H. Katevenis %O UCB/CSD 83/141 %D 1983 %S Computer Science Division %I University of California %C Berkeley, CA 94720 %K risc reduced instruction set computer architecture %X This is the Ph. D. thesis written by one of the designers of the RISC I & II. There is a nice summary of the RISC project, the rationale behind it, and implementation details of the RISC II chip. %l journal-article %A J. R. Larus %T A Comparison of Microcode, Assembly Code, and High-Level Languages on the VAX-11 and RISC I %J Computer Architecture News %V 10 %N 5 %M September %D 1982 %P 10-15 %K risc reduced instruction set computer architecture restricted %l journal-article %A J. Markoff %T RISC Chips %J Byte %V 9 %N 12 %P 191-206 %M November %K RISC %D 1984 %l journal-article %A V. McLellan %T IBM Mini a Radical Departure %J Datamation %V 25 %N 11 %P 53-55 %M October %K RISC %D 1979 %l journal-article %T The Case for the Reduced Instruction Set Computer %A D. A. Patterson %A D. R. Ditzel %J Computer Architecture News %V 8 %M Oct %D 1980 %K risc reduced instruction set computer restricted architecture %l proceedings-article %T RISC 1 : A Reduced Instruction Set VLSI Computer %A D. A. Patterson %A C. H. Sequin %J 8th. Ann. Symp. on Computer Architecture %M May %D 1981 %K risc reduced instruction set computer restricted architecture %l proceedings-article %A D. A. Patterson %A R. S. Piepho %T RISC Assessment: A High-Level Language Experiment %J 9th Symp. on Computer Architecture %M April %D 1982 %P 3-8 %K risc reduced instruction set computer architecture restricted %l journal-article %A D. A. Patterson %A C. H. Sequin %T A VLSI RISC %J Computer %V 15 %N 9 %M September %D 1982 %P 8-21 %K risc reduced instruction set computer architecture restricted %l proceedings-article %A D. A. Patterson %T A RISCy APPROACH TO COMPUTER DESIGN %J COMPCON %M Spring %D 1982 %P 8-14 %I IEEE Computer Society press %K risc reduced instruction set computer architecture restricted %l proceedings-article %A D. A. Patterson %A P. Garrison %A M. Hill %A D. Lioupis %A C. Nyberg %A T. Sippel %A K. Van Dyke %T Architecture of a VLSI Instruction Cache for a RISC %J Int. Symp. on Computer Architecture %D 1983 %P 108 %K fault tolerance associative memory SAMOS %K remote program counter jump branch likely bit %l journal-article %A D. A. Patterson %T RISC Watch %J Computer Architecture News %V 12 %N 1 %M March %D 1984 %P 11-19 %K reduced instruction set computer benchmarks %l journal-article %A G. Radin %T The 801 Minicomputer %J IBM J. Res. Dev. %D 1983 %V 27 %N 3 %P 237 %K RISC computer architecture IBM 801 cache %l journal-article %A P. U. Schultess %T A Reduced High-Level-Language Instruction Set %J Micro %V 4 %N 3 %M June %D 1984 %P 55-67 %K descriptor based addressing stack architecture reduced instruction set computer risc language directed %l journal-article %A P. Schulthess %A F. Vonaesch %T OPA - A New Architecture for Pascal-Like Languages %P 9 %K stack RISC language directed %J ACM Computer Architecture News %V 10 %N 6 %M Dec %D 1982 %l book-article %A C. H. Sequin %A D. A. Patterson %T Design and Implementation of RISC I %P 276-298 %K computer architecture register testing %l journal-article %T MOVE Architecture in Digital Computers %A Daniel Tabak %A G. J. Lipovski %J IEEE Trans. on Computers %V C-29 %N 2 %M February %D 1980 %P 180-189 %K RISC CMOVE architecture %l journal-article %T Strategies for Managing the Register File in RISC %A Y. Tamir %A C. H. Sequin %J IEEE Trans. on Computers %M Nov %D 1983 %K risc reduced instruction set computer restricted architecture %l proceedings-article %A D. Ungar %A R. Blau %A P. Foley %A D. Samples %A D. Patterson %T Architecture of SOAR: Smalltalk on a Risc %J 11th Annual International Symposium on Computer Architecture %I SIGARCH %D 1984 %P 188-197 %K object oriented architectures reduced instruction set architectures tagged object oriented architectures garbage collection %l proceedings-article %A Robert G. Wedig %T A Language-Oriented Approach for Implementing Branches: Structured Control Flow %J International Workshop on High-Level Computer Architecture %I Univ. of Maryland %M May %D 1984 %P 3. 1-3. 7 %K risc reduced instruction set computer restricted architecture %l journal-article %A M. V. Wilkes %T Keeping Jump Instructions out of the Pipeline of a RISC-Like Computer %J Computer Architecture News %I ACM %V 11 %N 5 %M Dec %D 1983 %P 5-7 //go.sysin dd * made=TRUE if [ $made = TRUE ]; then /bin/chmod 644 RISC /bin/echo -n ' '; /bin/ls -ld RISC fi