olson@fortune.UUCP (Dave Olson) (11/29/84)
The following (excerpted) article appeared in the 27 Nov 84
San Jose (Calif.) Mercury News. Does anyone have any more details?
Excerpt starts:
... Hitachi Ltd... is about a year way from unveiling a 32-bit
microprocessor, called the Micro 32.
... But now that the news is out, Hitachi plans on talking more about
it during its own technology conference Dec. 6 and 7 in New York City.
... sources say the ... chip has 400,000 transistors...
Most importantly, the Hitachi chip is expected to be upwardly
compatible with Motorola's 68000 chip. ....
End of excerpt.
Specifically, does anyone know if it is/will be upwardly compatible,
and what the new features will be?
Dave Olson, Fortune Systems
UUCP: {ihnp4,ucbvax!amd}!fortune!olson
ARPA: amd!fortune!olson@BERKELEYwall@fortune.UUCP (Jim Wall) (12/01/84)
The info on the new Hitachi chip is somewhat contradictory at this time. It is both a RISC chip and yet also is code compatible with the 68000!!! Two opposite ends of the spectrum. It is supposed on have an onboard MMU and cache controller, as well as an instruction cache. It is also supposed to come out at 20 MHz and go up to 40 MHz with future silicon. In other words, it is all on the drawing boards and is a long way off. -Jim
gjk@talcott.UUCP (Greg J Kuperberg) (12/02/84)
> > The info on the new Hitachi chip is somewhat contradictory at > this time. It is both a RISC chip and yet also is code compatible > with the 68000!!! Two opposite ends of the spectrum. > The 68000 is not very CISC or RISC. It is roughly in the middle between the two. To those of us that have been using Intel stuff for a few years, it looks RISC'y, but then again, Intel could be called FCISC (fucking complicated instruction set). --- Greg Kuperberg harvard!talcott!gjk "Eureka!" -Archimedes
davet@oakhill.UUCP (Dave Trissel) (12/04/84)
In article <4711@fortune.UUCP> wall@fortune.UUCP (Jim wall) writes: > > The info on the new Hitachi chip is somewhat contradictory at >this time. It is both a RISC chip and yet also is code compatible >with the 68000!!! Two opposite ends of the spectrum. > > It is supposed on have an onboard MMU and cache controller, as >well as an instruction cache. It is also supposed to come >out at 20 MHz and go up to 40 MHz with future silicon. In other >words, it is all on the drawing boards and is a long way off. > > -Jim *THIS ISNOT OFFICIAL MOTOROLA POLICY BUT MY OWN OPINION* In my opinion Hitachi is trying to *scare* Motorola into letting them second source the MC68020. They very well may have the plans they talk about on the drawing board, but don't hold your breath waiting for first silicon. I think the idea is *give us the 20 or we will just do something better.* I am not worried. Motorola Semiconductor Dave Trissel Austin, Texas 32-bit Applications Engineer