doug@oakhill.UUCP (Doug MacGregor) (12/14/84)
M68000 Architecture Analysis - Part III.a
Below are a few samples of the data that can be
obtained using this evaluation package. These examples are
from a variety of source data. They are intended as exam-
ples of the evaluations available and are not meant to be
taken as representative of the 68000 family. The first
information shown describes the average number of accesses
that take place during an instruction. These are described
in terms of the total number of accesses as well as the type
of accesses. In conjunction with the evaluation of the
68020 where the instruction cache provides some confusion,
it is possible to specify a cache hit rate or (as in the
example below) show the behavior for both the cache disabled
and the cache hitting 100% to see the range of activity.
Also shown are the percentages of the various types of
accesses. Finally, there is shown the number of clocks
required for execution for various number of wait states.
This figure can be used to derive the average number of
clocks per instruction by dividing the number of clocks by
the number of instructions shown at the top. These charac-
teristics can be observed for any processor in the family.
MC68020
Sample of 1000000. instructions
no cache cache
type of access access/inst access/inst
----------------------------------------------------------
total instruction accesses 0.957 0.000
total data reads 0.386 0.387
total data writes 0.244 0.244
total accesses 1.587 0.631
no cache cache
type of access percent percent
------------------------------------------------------
instruction accesses 60.311 0.000
data reads 24.319 61.351
data writes 15.370 38.649
# of wait states no cache clocks cache clocks
----------------------------------------------------------
0 - 7712343.5 - 6403860.5
1 - 9298905.0 - 7034788.0
2 - 10885471.0 - 7665718.5
3 - 12472027.0 - 8296648.5
4 - 14058602.0 - 8927580.0
5 - 15645174.0 - 9558510.0
6 - 17231740.0 - 10189435.0
7 - 18818300.0 - 10820366.0
8 - 20404854.0 - 11451297.0
9 - 21991436.0 - 12082221.0
10 - 23577988.0 - 12713153.0
11 - 25164560.0 - 13344083.0
12 - 26751122.0 - 13975011.0
13 - 28337688.0 - 14605933.0
The next plot shows the expected performance level for any
of the processors at any clock frequency at system access
times from 0 to 600ns. As above, the effect of the cache on
the 68020 can be either explicitly stated as a hit rate, or
the performance of the machine with and without the cache
can be observed. The performance is measured in terms of
68000 MIPS (millions of instructions executed per second).
This provides a reasonable performance measure between the
elements of the family. One of the goals of this study is
to better understand the relationship of a 68000 MIP to a
68020 MIP throughout various applications. For these plots
the system access time is measured as the time from valid
address to data.
PERFORMANCE ANALYSIS of MC68020 at various speeds
68000 Cache 100% Hit Rate 1 = 16.00Mhz 2 = 20.00Mhz 3 = 24.00Mhz
MIPS Sample of 1000000. instructions Cache Disabled a = 16.00Mhz b = 20.00Mhz c = 24.00Mhz
5.50 +
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5.00 +
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4.50 +
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4.00 +
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| 3333333333333
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3.50 +
| 33333333
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| ccccccccccccc2222 33333333
3.00 +
| 333333333
| 2222222222
| 33333333
| cccccccc 2222222222
2.50 + bbbbbbbbbbbbbbbbb111111 33333333
| 2222222222
| 33333333
| cccccccc1111111 2222222222 33333333
| bbbbbbbbbb 111111111111 333333333
2.00 + aaaaaaaaaaaaaaaaaaaaaaa 2222222222 33333333
| ccccccccc 1111111111111 2222222222 33333333
| bbbbbbbbbb 111111111111 2222222222 33333333
| aaaaaaaaaaaaa cccccccc 2222222222 33333333
| bbbbbbbbbb 111111111111 2222222222 333333333
1.50 + cccccccc 1111111111111 2222222222
| aaaaaaaaaaabbbbbbbcccccccc 1111111111111111111222
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| aaaaaaaaabbbbbcccccccc
| aaaaaabbbccccccccccccccccc
1.00 + aaaabbbbbbbbbbcccccccc
| aabbbbbbbbcccccccccccccccc
| aaaaaaaaabbbbccccccccc
| aaaaaaabbb
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0.50 +
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0.00 +
+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+
50 100 150 200 250 300 350 400 450 500 550 600
TOTAL SYSTEM ACCESS TIME - (ADDRESS TO DATA)
Similar to the performance plots, the plots of bus utiliza-
tion indicate the percentage of the bus that is utilized by
a particular processor over a given range of system access
times. As in other cases the 68020 cache characteristics
can be specified or as a default both disabled case and 100%
hit rates are provided. It is possible to see the introduc-
tion of wait states as system access time increases for a
particular processor and clock rate. The measurement of the
bus utilization can be useful in determining the behavior of
the processor in a system in which there are multiple pro-
cessors using a common bus, or in a system with multiple bus
masters
BUS UTILIZATION ANALYSIS of MC68020 at various speeds
Cache 100% Hit Rate 1 = 16.00Mhz 2 = 20.00Mhz 3 = 24.00Mhz
% of Bus Used Sample of 1000000. instructions Cache Disabled a = 16.00Mhz b = 20.00Mhz c = 24.00Mhz
100.0 +
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90.0 +
| cccccccccccccccccccccbb
| cccccccccccccccc bbbbbbbbbbbbbbbbbbbb
| ccccccccccccccbbbbbbbbbbbbbbbbbbbbaaaaaaaaaaaaaaaaaaaaaa
| cccccccc bbbbbbbbbb aaaaaaaaaaaaa
80.0 + cccccccc bbbbbbbbbb aaaaaaaaaaaa
| ccccccccbbbbbbbbbb aaaaaaaaaaaa
| cccccccbbbbbbbbbbaaaaaaaaaaaaa
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| cccccbbbbbbbbaaaaaaaaaaaa
70.0 +
| cccbbbbbaaaaaaaaaaaaa 3333333
| 3333333333333333 22
| 33333333 2222222222
| 33333333 2222222222
60.0 + aaaaaaaaaaaaaaaaaaaaaaa 333333333 2222222222 1111111111
| 33333333 2222222222 111111111111
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| 33333333 2222222222 1111111111111
| 33333333 2222222222 111111111111
50.0 +
| 333333332222222222 111111111111
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| 333333322222222221111111111111
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40.0 + 3333322222222111111111111
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| 333222221111111111111
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30.0 +
| 11111111111111111111111
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20.0 +
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10.0 +
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+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+
50 100 150 200 250 300 350 400 450 500 550 600
TOTAL SYSTEM ACCESS TIME - (ADDRESS TO DATA)
In the following tables the dynamic frequency and the
dynamic execution times for various categories of instruc-
tions and addressing modes are presented. The first table
provides a general breakdown of instruction categories.
This is elaborated upon in the second table where the type
of instruction are broken into categories with much greater
resolution.
GENERAL INSTRUCTION CLASSIFICATION
General Class Dynamic Freqency Dynamic Execution Time
----------------------------------------------------
MOVES = 33.51 = 32.42
BRANCH/JUMP = 23.95 = 26.34
CMP/TST = 11.13 = 11.55
ARITH/LOGICAL = 16.53 = 13.98
SUBROUTINE = 3.39 = 5.60
MISCELLANEOUS = 10.76 = 10.08
---------- ----------
Total 99.27 99.98
SPECIFIC INSTRUCTION CLASSIFICATION
General Class Dynamic Freqency Dynamic Execution Time
----------------------------------------------------
MOVES = 33.51 = 32.42
Move reg,reg = 3.05 = 0.96
Move reg,mem = 6.39 = 4.82
Move mem,reg = 16.06 = 17.29
Move mem,mem = 7.54 = 8.92
Movem = 0.03 = 0.15
Swap = 0.44 = 0.28
BRANCH/JUMP = 23.95 = 26.34
Bcc = 15.03 = 15.11
DBcc = 8.37 = 10.53
Jmp = 0.56 = 0.71
CMP/TST = 11.13 = 11.55
Cmp = 8.04 = 8.25
Tst = 3.09 = 3.31
ARITH/LOGICAL = 16.53 = 13.98
Arith/Logic = 8.04 = 8.25
Addx/Subx = 0.00 = 0.00
Eor = 0.30 = 0.10
Mul = 0.62 = 2.80
Div = 0.15 = 1.20
Shift = 2.93 = 1.87
Rotate = 0.38 = 0.24
Ext = 0.88 = 0.55
SUBROUTINE = 3.39 = 5.60
Bsr = 0.98 = 1.39
Jsr = 0.71 = 1.01
Rts = 1.69 = 3.19
MISCELLANEOUS = 10.76 = 10.08
Bit = 0.40 = 0.40
Clr = 2.82 = 2.57
Lea = 2.41 = 2.05
Pea = 1.93 = 2.15
Link = 1.38 = 1.09
Unlink = 1.38 = 1.31
Scc = 0.43 = 0.53
---------- ----------
Total 99.27 99.98
Both the source and destination addressing modes are
categorized. These categories can be a good indication of
how operands are being accessed and thus how the machine is
dealing with operands in memory and with registers.
SOURCE EFFECTIVE ADDRESSING MODES
General Class Dynamic Freqency Dynamic Execution Time
----------------------------------------------------
NONE = 35.35 = 36.38
REGISTER DIRECT = 12.74 = 8.76
Dn = 2.32 = 1.99
An = 1.47 = 1.14
Rn = 8.95 = 5.62
REGISTER INDIRECT = 28.66 = 34.75
(An) = 3.38 = 3.42
(An)+ = 4.20 = 4.64
-(An) = 0.06 = 0.08
(d,An) = 18.04 = 23.30
Calc (An) = 0.86 = 1.19
Calc (d,An) = 2.12 = 2.12
REGISTER INDEXED = 2.56 = 2.89
(d,An,Xn) = 0.80 = 1.20
Calc (d,An,Xn) = 1.76 = 1.69
ABSOLUTE = 0.54 = 0.66
xxx.w = 0.00 = 0.00
xxx.l = 0.00 = 0.00
Calc xxx.w = 0.14 = 0.15
Calc xxx.l = 0.40 = 0.51
PROGRAM RELATIVE = 0.34 = 0.29
(d,PC) = 0.01 = 0.06
Calc (d,PC) = 0.33 = 0.23
PROGRAM INDEXED = 0.01 = 0.02
(d,PC,Xn) = 0.00 = 0.00
Calc (d,PC,Xn) = 0.01 = 0.02
IMMEDIATE = 8.27 = 7.71
xxx = 7.07 = 7.33
Quick = 1.20 = 0.38
IMPLIED STACK = 3.08 = 4.50
(SP)+ = 3.08 = 4.50
---------- ----------
Total 91.55 95.96
DESTINATION EFFECTIVE ADDRESSING MODES
General Class Dynamic Freqency Dynamic Execution Time
----------------------------------------------------
NONE = 17.28 = 19.01
REGISTER DIRECT = 50.03 = 46.65
Dn = 24.53 = 23.01
An = 7.57 = 5.68
Rn = 17.93 = 17.96
REGISTER INDIRECT = 24.35 = 25.60
(An) = 1.79 = 1.83
(An)+ = 7.37 = 8.05
-(An) = 5.90 = 5.92
(d,An) = 9.28 = 9.81
REGISTER INDEXED = 1.99 = 2.88
(d,An,Xn) = 1.99 = 2.88
ABSOLUTE = 0.00 = 0.00
xxx.w = 0.00 = 0.00
xxx.l = 0.00 = 0.00
IMPLIED STACK = 5.02 = 5.66
(SP)+ = 5.02 = 5.66
---------- ----------
Total 98.66 99.81