vomlehn@ut-ngp.UUCP (vomlehn) (02/27/85)
I don't know about the 8087 using multi-valued logic internally, but I do know that there are some memory chips do. Dynamic memory cells are implemented as capacitors (basically) which don't care too much whether they hold one of two voltage values or one of four (which means you can store two bits in one cell). By spacing the four voltages sufficiently far apart you can get the same noise immunity without doubling the size of the cell. The circuitry needed to distinguish the four voltage levels apart and to generate them is roughly twice as complex, but only needs to appear once in each column of memory cells. Since there may be a few hundred cells in a column, this is a very small overhead to pay. One application of multi-valued logic which I have never heard of is voltage- multiplexing pins. One of the major problems facing chip manufacturers is having to use an ever-increasing number of pins on their chips. There are chips now having 160+ pins. This increases the difficulty of producing the chip by a fair margin. Some chip makers time-multiplexed pins, so that the same set of pins may have address information during one time interval and data information during the next. If the pins were voltage-multiplexed a given pin would only contain data, but it would contain the data for two logical data lines. For example, take a given data pin, with two logical data lines: Logical line 1 Logical line 2 Value on pin -------------- -------------- ------------- false false 0 volts false true 1 volt true false 2 volts true true 3 volts With this scheme the number of data and address pins could easily be halved. The time overhead for time-multiplexing is non-trivial, since you have to switch the lines twice to perform a given task, resulting in twice the settling delays and the need to decode which information is to be processed. By voltage-multiplexing there may be a small overhead due to feeding two logical lines into an interface circuit to result in one of four voltage values on a pin and more overhead to break four voltage values into two logical lines, but this overhead would be much smaller than that for time-multiplexing. With some clever design, the multiplexing might be done with no time cost if the circuit can do some processing with multi-valued logic. The key disadvantage to this scheme is that it introduces a need for a new type of "glue" chip - one which can take voltage-multiplexed values and break them into their constituent logical values and another which reverses the process, but these chips would be pretty trivial. I'd guess that they would be no more complex than the average 7400-series chip and have a comparable cost. If a chip maker comes out with a line of components which all use the same voltage-multiplexing technique, no glue chips would be needed when inter- connecting these chips and the corresponding reduction in pins and traces on the printed circuit board would pay off pretty quickly. David M. VomLehn vomlehn@ut-ngp.ARPA ...decvax!ihnp4!ut-ngp!vomlehn
crandell@ut-sally.UUCP (Jim Crandell) (03/01/85)
> I don't know about the 8087 using multi-valued logic internally, but I do > know that there are some memory chips do.... > > One application of multi-valued logic which I have never heard of is voltage- > multiplexing pins. Interesting juxtaposition. Have a look at the MM5270 (18-pin, 4K dynamic RAM). Three levels on one pin, I readily admit, doesn't look very impressive, but it enabled them to get a nonmultiplexed 4-K into 18 pins. You gotta start somewhere. -- Jim Crandell, C. S. Dept., The University of Texas at Austin {ihnp4,seismo,ctvax}!ut-sally!crandell
yamauchi@fortune.UUCP (Alan Yamauchi) (03/01/85)
In article <1384@ut-ngp.UUCP> vomlehn@ut-ngp.UUCP (vomlehn) writes: > >One application of multi-valued logic which I have never heard of is voltage- >multiplexing pins. . . . Some chip makers time-multiplexed pins, so that the >same set of pins may have address information during one time interval and >data information during the next. If the pins were voltage-multiplexed >a given pin would only contain data, but it would contain the data for two >logical data lines. Voltage multiplexed pins are already being implemented at some of the semi- conductor houses now, although not quite in the manner you suggested. This is done strictly for in house test purposes and mostly with the more complex parts such as uComputers and uProcessors. Applying voltages > 7V to certain pins on these parts allows the testers to dump either internal masked ROM or uCode. I'm not sure of exact voltage levels necessary to change the functionality of pins, but some other semi houses use an alternate method of dumping ROM or uCode, such as forcing certain opcodes in special sequences. Of course most of this in not common knowledge unless you've either worked in or are working in a semiconductor house. The technology to do what you suggest certainly exists, but to do it commercially in the bi-level logic world now would be quite costly. \ / Alan Yamauchi * \___/ UUCP: {ihnp4,ucbvax!amd,hpda,sri-unix,harpo}!fortune!yamauchi DDD: (415)594-2436 USPS: Fortune Systems Corp, 101 Twin Dolphin Drive, Redwood City, CA 94065