mwm@ucbtopaz.CC.Berkeley.ARPA (03/16/85)
Having finally read the CACM article on the Cosmic Cube, I can't help but notice the similarity betweent the projected "node machine" and the transputer chips. Could someone knowledgeable about both please comment on how well such chips would go into a cube architechture? Thanx, <mike
ian@loral.UUCP (Ian Kaplan) (03/20/85)
The Transputer has four bit serial I/O channels, so that you could build
at most a 4-D cube (each node in the cube network has connections to
four other processors). The Cosmic Cube and the iNTEL iPSC are 6-D
cubes. The Transputer is designed for 2-D processor arrays. Arrays of
this sort are usually used in systolic and pipelined array processing
applications. NCR has already had some success in this area (See
"Systolic Array Chip Matches the Pace of High-speed Processing", a four
part serries in Electronic Design, Oct. 31 through December 13).
Inmos seems to claim more utility for the Transputer than I have outlined
above, but I have not seen any information to back this claim.
Inmos has also been claiming that their Occam language is a great
break through in parallel processing languages. I believe that an
examination of the Occam programmer's manual ("Occam Programming
Manual", INMOS Limited, Prentice-Hall International) is sufficient to
dispel INMOS's claims.
Also, last I heard, the Transputer was *still* not available.
Disclaimer and all that:
Occum and INMOS are trademarks of the Inmost Group of Companies.
The opinions expressed here are entirely my own and do not reflect
official opinion of Loral Instrumentation. Affiliation is included for
purposes of identification only.
Ian Kaplan
Loral Data Flow Group
Loral Instrumentation
(619) 560-5888 x4812
USENET: {ucbvax,decvax,ihnp4}!sdcsvax!sdcc6!loral!ian
ARPA: sdcc6!loral!ian@UCSD
USPS: 8401 Aero Dr. San Diego, CA 92123jww@bonnie.UUCP (Joel West) (03/21/85)
> The Transputer has four bit serial I/O channels, so that you could build > at most a 4-D cube (each node in the cube network has connections to > four other processors). The Cosmic Cube and the iNTEL iPSC are 6-D > cubes. Actually the iPSC ranges from 5-D to 7-D. The Caltech folks, true, have only built a 6-d, but their whole design approach and philosophy has been to support N-d. I'm sure they will build a 7- or 8- within a year, and there are those there who'd like a 10-D cube of 8086's. But, I agree, the current Transputer is impractical for cube design. It is claimed that future version will have more i/o channels. If it did, it might be worth using for a Cosmic Cube, as nwm@ucbtopaz first suggested. The current T424 transputer claims 750 kbytes/sec vs 250 kb/s for the Cosmic Cube, not a spectacular improvement--particularly compared to the 4 mbytes/sec bandwidth of each channel on the DARPA-BBN "Butterfly". However, as Caltech has planned all along, the Cosmic Cube design will best be implemented in a single chip per node. The size of the Cosmic and iPSC alone are impractical in the long run for larger networks. But with a chip-based node, a 10-cube in a file cabinet becomes feasible. Whether it's a transputer or a "connection machine" or something from Caltech, I dunno. > Inmos has also been claiming that their Occam language is a great > breakthrough in parallel processing languages. I believe that an > examination of the Occam programmer's manual ("Occam Programming > Manual", INMOS Limited, Prentice-Hall International) is sufficient to > dispel INMOS's claims. > > Ian Kaplan > Loral Data Flow Group > USENET: {ucbvax,decvax,ihnp4}!sdcsvax!sdcc6!loral!ian The 50? 80? page book is overpriced at $20. And the claims made about how everyone should use Occam for everything -- systems programming, scientific, engineering, simulation, etc. -- are overrated. The world doesn't need another completely new language. It has several thousand already, all but 20 of which are not used by more than 100 people in the world. Occam has some nifty ideas, but those could be re-implemented around C (another portable assembly language). The rest of Occam is just someone's idea of idiosyncratic "innovation." -- Joel West (619) 457-9681 CACI, Inc. - Federal 3344 N. Torrey Pines Ct La Jolla 92037 jww@bonnie.UUCP (ihnp4!bonnie!jww) westjw@nosc.ARPA "The best is the enemy of the good" - A. Mullarney
lwe3207@acf4.UUCP (Lars Warren Ericson) (03/22/85)
[] In defense of INMOS, one could well imagine multiplexing each of their 1.8 MBytes/sec channels to get an 8 port machine. One can also tie ports in as memory devices, just like in PDP-11's. It is a new processor, and as usual with new processors, it takes a while for them to get the bugs out. I believe they are prepared to sell emulation boards for evaluation, and they do have the Occam Programming System for the VAX. I am using this system at NYU. Occam *is* a new language: it is CSP, implemented. It is quite different, and quite simple. Of course, that means that in the next version, new features will be added. But there are very few languages that let you set down, and in a few lines, without extensive declaration of message structures, tasks, modules, 10-clause ACCEPT statements, etc., do concurrent programming. The following is a summary of my last conversation with the Tech/Sales Reps (I am not an employee of INMOS: I just like their stuff & find them helpful): -- Lars Ericson, NYU CS Dept. -- ...!cmcl2!csd1!ericson -- ericson@nyu SOFTWARE Proto-Occam, $100 demo kit. We bought it. Occam Programming System, editor&compiler, $100. We bought it. Version II, coming in a month, with multi-dimensional arrays, 8,16,32-bit integers, IEEE floating point, strong typing with explicit coercions, separate compilation, and the ability to "vectorize" procedures and data in a type-unsafe way so that they can be shipped down channels. Some bugs in parameter passing and vector referencing in the current system. Occam Porta-Kit. $100. They give you the compiler up to the intermediate-code level; you supply the rest. Minimal license, doesn't require signing: you mail the whole thing back if you can't abide by it. HARDWARE Emulation board. 1 Meg memory, $2000. Somewhere around now. Chip. 84 pins, $500. "Second half". Previous estimate (1 month ago) "3rd quarter". 4 data channels, 1 memory channel, both run about 1.8 mbyte/sec, 4k static ram on board. Data sheet available. CONTACTS Sales Rep, Susan Woster, (303) 630-4660. Tech Rep (for compiler bugs, etc.), Pete Wilson, (303) 630-4256.
gjerawlins@watdaisy.UUCP (Gregory J.E. Rawlins) (03/24/85)
I would appreciate it if the posters to this particular
discussion would remove net.chess from the distribution list. The
original article could be said to be vaguely connected with chess
but the discussion quickly became pure architecture, help stamp
out the use of the 'n' key by posting articles to the relevant
news groups. thanks.
--
Gregory Rawlins CS Dept.,U.Waterloo,Waterloo,Ont.N2L3G1 (519)884-3852
gjerawlins%watdaisy@waterloo.csnet CSNET
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