brando@linus.UUCP (Thom Brando) (03/21/85)
*** REPLACE THIS LINE WITH YOUR MESSAGE *** Sorry for the delay in posting this, but Perry Scott's articel was dumped into newsgroup "junk" here, and I just began looking at junk today! In <268@oliveb.UUCP> Jerry Aguirre (jerry@oliveb) said: > If your (sic) thinking that 1M processors is unreasonable then think again. In <1500003@hp-dcde.UUCP> Perry Scott (perry@dp-dcde or perry-s@hpfcla???) responded with: >Although it makes sense to put entire chipsets on the same wafer, you're >going to run up against several problems: > >1) Heat dissipation... Although I don't know the maximum amount of heat > that a wafer can dissipate, it would appear that even 4 CPU/RAM's would > be pushing it. > >2) Yield. As circuit complexity increases, yield decreases. Having all those > circuits be correct simultaneously may be a statistical impossibility. > >3) Cost. If (1) requires different (more expensive) cooling technology, and > (2) makes yields even lower, the volume price would still be higher. Consider, however, the possibilities of constructing a network of a million processors not with today's technology, but with technology that will be available in the near future. High-density, low-power technology is here, or very nearly here, as is wafer-scale integration. I've been told that at last year's ICCD conference held in Port Chester, NY, one company claimed to be able to stack wafers 8 per inch using freon cooling. Now consider the possibility of laying out a rectangular grid of, say, 16 x 16 = 256 processors-with-memory on a wafer. I've been told this is not unreasonable to expect: most of the heat generated by a chip is a result of circuitry for getting on and off the chip (and, therefore, goes away when you communicate on-wafer); as far as yield is concerned... if the processors are identical, and if a failed processor doesn't affect the correct functioning of other processors, then yield doesn't suffer. (Of course you can't expect an entire wafer to be defect free, but if the defects only mean that small areas around the defects are nonfunctioning, and the remainder of the circuits on the wafer are still operational, then so what?) Now consider connecting wafers in a 16 x 16 grid - call that a rack. Now stack 16 racks together (in a space of 2 inches ?!) and you've got a total of 16 x 16 x 16 x 16 x 16 = 1M processors. People I've spoken with say there's no reason to expect it won't be possible with the technologies I've mentioned. The only question left is how to interconnect the processors on a wafer, the wafers in a rack, and the 16 racks to support massively parallel operation (read "I/O intensive operation"). There are ways... at least that's what many people believe. And until we've learned otherwise, that's the assumption that many of us are working under. The opinions expressed above are my own and also those of a number of people with whom I labor in the salt mines... Thom Brando (617) 271-3156 m/s E030, The MITRE Corp, Burlington Road, Bedford MA 01730 {decvax,utzoo,philabs}!linus!brando.UUCP
brando@linus.UUCP (Thom Brando) (03/21/85)
By the way... if the concept of assembling a million processors excites
you, either pro or con, you might want to check out this year's ICCD
conference, coming up in October.
Thom Brando {decvax,utzoo,philabs}!linus!brando.UUCPhenry@utzoo.UUCP (Henry Spencer) (03/25/85)
> Consider, however, the possibilities of constructing a network of a million > processors not with today's technology, but with technology that will be > available in the near future. High-density, low-power technology is here, or > very nearly here, as is wafer-scale integration... Not to be skeptical or anything, but wafer-scale integration has been "very nearly here" for a number of years now. -- Henry Spencer @ U of Toronto Zoology {allegra,ihnp4,linus,decvax}!utzoo!henry