jeff@abnji.UUCP (jeff) (05/20/85)
[interrupt request acknowledged!] An honest question: When a cpu (such as the 8086, 68k,etc) acknowledges a bus request, does it halt internal execution with the bus acknowledge, or after the bus acknowledge only when bus activity is needed (deferring prefetch if necessary)? example: The instruction queue/cache is full of register to register (or other internal) instructions when the bus request is acknowledged. Will it execute them while the bus is relinquished? Chips with on-chip cache can do a lot with no external bus action. Did anyone bother to make the control section sophisticated enough to handle this? It would be a real boon to multi-processor applications! I see that the reasoning to on-chip memory and peripherals is so the local and global busses can be relinquished and still have the CPU do some non-trivial work, as well as a speed advantage and less synchronization. Is anyone using this capability to its fullest? Jeff 'I really wanna know' Skot at foggy ATT IS Somerset, NJ {ihnp4 | mcnc | cbosgb} abnji ! jeff
gnu@sun.uucp (John Gilmore) (06/03/85)
In the 68020, when the bus is granted to a DMA device, the CPU continues to fetch and execute instructions. If a prefetch misses the on-chip instruction cache, or a data reference occurs, it will hang; otherwise, it will continue execution. The 68000 and 68010 would continue executing instructions like multiply or shift while the bus was granted, but would hang immediately after the instruction finished because it had to fetch another. In general, any CPU that doesn't have an on-chip cache will have to stop pretty soon. Unless the bus is a lot faster than the CPU (they were about evenly matched in the 68000; I hear the CPU was faster than the bus in the 8086 and especially in the 8088), the prefetch queue will not be very full, so even a chip with a deep prefetch will stall pretty soon. Of course, if you are only stealing one DMA cycle then you might luck out; but it's more efficient to steal 20 DMA cycles at once than to steal one 20 times, since you lose a lot in arbitration delays. Signetics has an interesting part in design called the MAC (Memory Access Controller) for 680xx family parts. It's an MMU which manages a local cache memory. It lets you map each page of main memory as "local" or "global" memory to keep the global bus traffic separate. It kind of does what you are talking about on a multiprocessor level rather than on a CPU chip level.