mash@mips.UUCP (John Mashey) (06/03/85)
Darrell Long writes: > The BELLMAC-32 processor (a.k.a. WE-3200x) has an > instruction, called RESTORE which restores a set of regis- > ters from the stack. ..... However, the as assembler > insists on mapping this single instruction to up to 7 > instructions. Dave Poplawski replies: > The reason the assembler gives the sequence instead of the single RESTORE > instruction is because of a chip bug. I don't remember the exact problem, > but as I recall, if a page fault happened when the instruction was > executing a timing problem in the chip would cause the WRONG registers to > be restored.... There have been various discussions of RISC pros and cons lately in net.arch. One of the strongest, most least discussed motivations for RISC is the hope of getting exception-handling right earlier. This area seems inevitably to be the one that breaks chips, especially ones with complex instructions, heavy pipelining, etc. Certainly the currently popular chips have had their share, and this is not new. Unless memory fails me, I recall we had trouble with PDP-11/45s where the wrong combination of stack underflow and some addressing mode (which UNIX happened to use, but DEC didn't) caused wrong values to be saved....Anybody have any other examples where chip or cpu revs were caused by flawed exception handling? -- -john mashey UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mash DDD: 415-960-1200 USPS: MIPS Computer Systems, 1330 Charleston Rd, Mtn View, CA 94043