darrell@sdcsvax.UUCP (Darrell Long) (05/29/85)
Well folks, here I am again with 3B-2 assembler com-
ments, questions and gripes. My topic tonight is the
RESTORE instruction.
The BELLMAC-32 processor (a.k.a. WE-3200x) has an
instruction, called RESTORE which restores a set of regis-
ters from the stack. This instruction really exists, I
typed in the hex code for it. However, the as assembler
insists on mapping this single instruction to up to 7
instructions.
RESTORE => MOVAW
POPW
...
POPW
This is a strange thing for an assembler to do. Is it
done so that the same assembler can be used on a processor
which does not have the RESTORE instruction? Or is it that
the sequence of POPW instructions are actually faster than
the RESTORE (if this is true then why waste chip space with
the RESTORE instruction)?
--
Darrell Long
Department of Electrical Engineering and Computer Science
University of California, San Diego
USENET: sdcsvax!darrell
ARPA: darrell@sdcsvaxpop@mtu.UUCP (Dave Poplawski) (06/01/85)
The reason the assembler gives the sequence instead of the single RESTORE
instruction is because of a chip bug. I don't remember the exact problem,
but as I recall, if a page fault happened when the instruction was
executing a timing problem in the chip would cause the WRONG registers to
be restored. It was easier (schedule-wise) to fix the assembler than to
fix the chip. Hopefully this will be fixed in future versions of the chip
- it should help performance a bit.
--
Dave Poplawski
Michigan Technological University
uucp: {lanl, ihnp4, glacier}!mtu!pop
arpa/csnet: pop%mtu@csnet-relayksbszabo@wateng.UUCP (Kevin Szabo) (06/02/85)
> The BELLMAC-32 processor (a.k.a. WE-3200x) has an >instruction, called RESTORE which restores a set of regis- >ters from the stack....... However, the as assembler >insists on mapping this single instruction to up to 7 >instructions.......??? Another possibility is that the RESTORE instruction might not operate properly for all CPU's. Maybe the assembler is working around a buggy mask set? Kevin -- Kevin Szabo watmath!wateng!ksbszabo (U of Waterloo VLSI Group, Waterloo Ont.)
brt@whuts.UUCP (B Reytblat) (06/03/85)
> > The BELLMAC-32 processor (a.k.a. WE-3200x) has an > >instruction, called RESTORE which restores a set of regis- > >ters from the stack....... However, the as assembler > >insists on mapping this single instruction to up to 7 > >instructions.......??? > > Another possibility is that the RESTORE instruction > might not operate properly for all CPU's. Maybe the assembler is working > around a buggy mask set? > Kevin > -- > Kevin Szabo watmath!wateng!ksbszabo (U of Waterloo VLSI Group, Waterloo Ont.) *** REPLACE THIS MESSAGE WITH YOUR LINE *** I have not yet had an opportunity to talk to Darryl Long (the poster of the original article). I would, however, like to respond to Kevin's suggestion: It is most emphatically NOT the case ! The RESTORE instruction does operate properly on all WE 3200x* Microprocessors I have ever tried (several 3B2's, one 3B5 and a bunch of WE 320EB's and WE 320AP's). Here's a little exercise I have just performed (I'm running on an Amdhal w/ Sys 5 and the following version of WE3200x Microprocessor Tools: m32: command -Release 5.0.1.2 4/25/82 for (3B2) ) Source: main() { int a; a ++; } I do "m32cc -S try1.c" and get back try1.s: .file "try1.c" .data .text .align 4 .def main; .val main; .scl 2; .type 044; .endef .globl main main: save &.R1 addw2 &.F1,%sp addw2 &1,0(%fp) .L12: .set .R1,0 ret &.R1 .set .F1,4 .def main; .val .; .scl -1; .endef .data **** m32 DISASSEMBLER **** I then do "m32cc -c try1.s; m32dis try1.o" and get back : disassembly for try1.o section .text main() 0: 10 49 SAVE %fp 2: 9c 4f 04 00 00 00 4c ADDW2 &0x4,%sp 9: 90 59 INCW 0(%fp) b: 70 NOP c: 18 49 RESTORE %fp e: 08 RET f: 70 NOP As you can see, the IS25 instruction "ret &.R1" got translated into two WE3200x Microprocessor instructions: "RESTORE %fp" and "RET". NOT a bunch of POP's !!! I don't understand how Darryl is running into his problem, but would be glad to talk to him, or anyone else about it. My phone number is (201)-981-2044. Hope this helps, Ben Reytblat. AT&T Bell Laboratories. * WE is a registered trademark of AT&T Technologies
brooks@lll-crg.ARPA (Eugene D. Brooks III) (06/04/85)
> > The BELLMAC-32 processor (a.k.a. WE-3200x) has an > >instruction, called RESTORE which restores a set of regis- > >ters from the stack....... However, the as assembler > >insists on mapping this single instruction to up to 7 > >instructions.......??? > > Another possibility is that the RESTORE instruction > might not operate properly for all CPU's. Maybe the assembler is working > around a buggy mask set? > Kevin Yet more proof that they should have designed a RISC!
crandell@ut-sally.UUCP (Jim Crandell) (06/05/85)
> > > The BELLMAC-32 processor (a.k.a. WE-3200x) has an > > >instruction, called RESTORE which restores a set of regis- > > >ters from the stack....... However, the as assembler > > >insists on mapping this single instruction to up to 7 > > >instructions.......??? > > > > Another possibility is that the RESTORE instruction > > might not operate properly for all CPU's. Maybe the assembler is working > > around a buggy mask set? > > Kevin > Yet more proof that they should have designed a RISC! Intentionally, you mean. -- Jim Crandell, C. S. Dept., The University of Texas at Austin {ihnp4,seismo,ctvax}!ut-sally!crandell
jer@peora.UUCP (J. Eric Roskos) (06/10/85)
>> Another possibility is that the RESTORE instruction >> might not operate properly for all CPU's. Maybe the assembler is working >> around a buggy mask set? >> Kevin >Yet more proof that they should have designed a RISC! No, proof they should have designed a machine with writable control store... -- Full-Name: J. Eric Roskos UUCP: ..!{decvax,ucbvax,ihnp4}!vax135!petsd!peora!jer US Mail: MS 795; Perkin-Elmer SDC; 2486 Sand Lake Road, Orlando, FL 32809-7642 "Erny vfgf qba'g hfr Xbqnpuebzr."