crowley@ihlpm.UUCP (Opus) (06/11/85)
In the June 1985 issue of VLSI Design magazine there is an article titled "PLDs As Semicustom Substitutes". This article discusses the cost to develop programmable logic devices (PLDs), gate arrays, and standard cells. It stated that gate arrays are cheaper to develop than standard cells. Could someone explain why this is? I always thought that standard cells would be cheaper because of being able to use function blocks in the design of it. Gate arrays would be more expensive because of using gate level blocks to design it. Bob Crowley ihlpm!crowley Bell Labs - Naperville send all flames to /dev/`tty` (:-))
ksbszabo@wateng.UUCP (Kevin Szabo) (06/12/85)
In article <291@ihlpm.UUCP> crowley@ihlpm.UUCP (Opus) writes: > It stated that gate arrays are cheaper to >develop than standard cells. Could someone explain why this is? >I always thought that standard cells would be cheaper because >of being able to use function blocks in the design of it. >Gate arrays would be more expensive because of using gate level >blocks to design it. Short but sweet...gate arrays are pre-arranged transistors interconnected as gates. They are predesigned and prefabricated just up to the point of adding the metalization. The designer determines his wiring list and that is mapped onto the metallization layer. In standard cell design the standard cells are functional blocks (ram, nand alu's etc) that are chosen by the designer and interconnected. Note that this chip cannot be prefabricated, it must have a full complement of masks made for each design. The photolithography cost and the inability to prefabricate the chip are the major costs. Gate array's are harder to use since you have to "map your problem to the solution" but they have the fastest turn around time of all the VLSI design techniques. I can elaborate a little more if you want. Kevin -- Kevin Szabo' watmath!wateng!ksbszabo (U of W VLSI Group, Waterloo, Ont, Canada)
mfe@leadsv.UUCP (Mark Ellson) (06/12/85)
In article <291@ihlpm.UUCP>, crowley@ihlpm.UUCP (Opus) writes: > In the June 1985 issue of VLSI Design magazine there is an article > titled "PLDs As Semicustom Substitutes". This article discusses the > cost to develop programmable logic devices (PLDs), gate arrays, > and standard cells. It stated that gate arrays are cheaper to > develop than standard cells. Could someone explain why this is? In designing any semi-custom chip, either gate array or standard cell, you will typically use a set of functional blocks or macro cells which have been provided by your foundry. In a standard cell design, the macro cells have been compacted to minimize size within the constraint of having a fixed height but with variable width. In gate arrays, the macro library may exist only at the netlist level (a soft macro), or the foundries layout tools may require that all of the gates in a macro be grouped together with a specific metallization pattern (a hard macro). The hard macro will typically give you better performance for the cell since all of the internal delays are known, and hopefully minimized. The advantage of a soft macro is more flexibility in routing the metallization. The real savings in designing gate arrays is in the reduced layout times because all you are concerned with is the final metallization, and reduced tooling costs because you need substantially fewer masks to produce your design. Also, the turn around time for gate array prototypes is generally about 4 weeks shorter. In many of the designs which we do here this quicker turn around is really the deciding factor in favor of gate arrays. Mark Ellson Lockheed Missiles & Space Co. ucbvax!sun!sunncal! \ > leadsv!mfe ihnp4!amd!cae780! /