[net.arch] Bus locking for memory-to-memory instructions on multis.

patrick@mcc-db.UUCP (Patrick McGehearty) (06/17/85)

C.mmp (a multi-PDP11 machine built at CMU in the 70's) locked the
targeted memory bank (one of 16) during a Read-Modify-Write instruction.
The decision to lock on all RMW instructions instead of just test-and-set,
or compare-and-swap or increment or ... was made early in design to
allow the OS implementors freedom to experiment with alternate methods
of synchronization.

As an adjunct to my thesis on performance evaluation of C.mmp, I built
a detailed simulation model of the C.mmp processor/memory behavior.
This model indicated that locking on all RMW instructions had a
significant effect on memory contention and system performance.
The exact effect depends on many factors, such as processor vs memory
speed, size of crosspoint switch, randomness of memory references,
presences of cache, etc.

The conclusion is that to obtain peak performance, one should only
provide memory locking for a selected set of instructions which are
used primarily for synchronization.
(Alternate conclusion: lock on very small units of memory to minimize
collisions like the HEP does)