kds@intelca.UUCP (Ken Shoemaker) (06/20/85)
> A memory-protected 68K box need not be slow nor expensive. The 68K
Cheap and expensive are relative terms, however the last time I looked,
the board real-estate for an external MMU was certainly greater than that
of an on-chip MMU, and the fact that it requires extra hardware would
tend to make me believe that it probably isn't cheaper from a raw component
cost, from an assembly cost, a testing cost or from a stocking cost.
As for performance, there are a few tacks that can be taken. The problem is
that you don't get all the address bits out when the processor gives
them to you, since some of them have to go through you MMU, and an
external MMU requires > 0 translation/drive time! These either limit
your flexibility in system expansion (e.g., differentiated row/column
addresses to memory) or they add even more to the system cost (e.g.,
a virtual address cache).
On the topic of multiprocessor systems and locked buses, the 286 allows
instructions that perform read-modify-write operations to lock the bus
selectively through the use of the "lock" prefix. Thus, the instruction
lock add word ptr [0],blah
would add "blah" to the word in memory at location 0, and would prevent
other processors from gaining access to memory between the read @0 and
the write to 0. Although this is a little unusual (the usual use for
lock is to check semaphores), I can see how it could be useful, and
I would be very suprised if the 68K of the 32K (or any other micro
out there) didn't provide a similar facility (e.g., more than just
a simple bus locked test and set instruction).
--
...and I'm sure it wouldn't interest anybody outside of a small circle
of friends...
Ken Shoemaker, Microprocessor Design for a large, Silicon Valley firm
{pur-ee,hplabs,amd,scgvaxd,dual,qantel}!intelca!kds
---the above views are personal. They may not represent those of the
employer of its submitter.