bcase@uiucdcs.Uiuc.ARPA (07/18/85)
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Question for you AT&T guys (or anyone who knows): The WE32100 documentation
has a block diagram of the internal organization of the data path. Does this
block diagram accurately reflect the data flow? Specifically, the register
file seems to have only one port going to the ALU; if this is true, it would
seem to mean that a register-register add would take three cycles: read
first register to temp, read second register and temp and add, and store back
the computed result (I suppose it could take even more cycles if the register
read and compute cannot be done in one cycle). This "one bus" architecture
is quite similar (if it is indeed correct) to the architecture of the NS320xx
series. If the internals are organized as I have outlined, why? Was there
insufficient area for more buses and all the other necessary stuff?
Thanks in advance -
Brian Case
bcase@uiucdcs.UUCP