levy@ttrdc.UUCP (Daniel R. Levy) (07/25/85)
ss@sjuvax.UUCP (J. Shapiro) <1202@sjuvax.UUCP> quotes and tells us: >> > But hardware multiplies invariably generate a two word result, leaving the >> > high-order word to be allowed for and/or disposed of. >> >> The Decsystem-10 & 20 has an instruction IMUL which does exactly what you >> want. It Multiplies a 36bit value by another 36 bit value and gives a 36 >> bit result. They also have a divide which divides a 36 bit number. > >For comparison and elucidation, so do: > > VAX > PDP-11 > National 32016 and family > Motorola 68000, 68020, 6800, 6809, ... ^^^^ > Zilog Z8000 > Z80 > Intel 8086, 80186, 82086 Since when did Motorola add such fancy hardware to their lowly 6800? -- ------------------------------- Disclaimer: The views contained herein are | dan levy | yvel nad | my own and are not at all those of my em- | an engihacker @ | ployer, my pets, my plants, my boss, or the | at&t computer systems division | s.a. of any computer upon which I may hack. | skokie, illinois | | "go for it" | Path: ..!ihnp4!ttrdc!levy -------------------------------- or: ..!ihnp4!iheds!ttbcad!levy
jeff@gatech.CSNET (Jeff Lee) (07/26/85)
>>> The Decsystem-10 & 20 has an instruction IMUL which does exactly what you >>> want. It Multiplies a 36bit value by another 36 bit value and gives a 36 >>> bit result. They also have a divide which divides a 36 bit number. >> >>For comparison and elucidation, so do: >> >> ... >> Motorola 68000, 68020, 6800, 6809, ... >> ^^^^ >> ... > > Since when did Motorola add such fancy hardware to their lowly 6800? I remember the 6801 having an 8x8 bit multiply but it put the result in the D register (A and B used as a double length register), giving a 16-bit result. -- Jeff Lee CSNet: Jeff @ GATech ARPA: Jeff%GATech.CSNet @ CSNet-Relay.ARPA uucp: ...!{akgua,allegra,hplabs,ihnp4,linus,seismo,ulysses}!gatech!jeff