[net.arch] RISC and MIP

phil@amdcad.UUCP (Phil Ngai) (07/30/85)

Just what is a MIP, anyway? Million Instructions Per?
Perhaps you mean MIPS, as in "the VAX 780 is rated at 1 MIPS".

My reference (and I am sure there are many others) is section 1.5.1 "MIPS"
of "Computer Storage Systems and Technology", by Richard Matick of IBM.
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 Phil Ngai (408) 749-5720
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armstron@sjuvax.UUCP (L. Armstrong) (08/02/85)

> Just what is a MIP, anyway? Million Instructions Per?
> Perhaps you mean MIPS, as in "the VAX 780 is rated at 1 MIPS".

I just kinda' jumped into this discussion, but I have a feeling I know what
you're talking about anyway.  A "MIPS" can (and in fact does) refer to something
more than Million Instructions Per Second", but also to a type of architecture
philosphy called "Microprocessor without Interlocked Pipe(line) Stages."  It
is originally a Stanford project, initiated by Thomas Gross, and in a nutshell
the philosphy attempts to avoid ever having to "flush" out a pipeline if (for
example) a certain brach is taken, and the things currently existing in the
pipeline are no longer applicable.

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