gnu@sun.uucp (John Gilmore) (08/09/85)
> Is there any architectural reason why Motorola at some future date > could not issue a 6802x with a larger instruction cache? It's well enough designed that they could change it between this month's rev of the chip and next month's, if they wanted to. Software would have to do some abnormal things to DETERMINE the cache size. (Of course you could tell to some degree by performance.)