wildstar@nmtvax.UUCP (10/16/85)
I had an idea about creating a systolic machine, but it might not seem to follow any orthodox rules. I would like to build a PROLOG machine capable of spawning off processes in parallel instead of performing backtracking. The way I thought of doing it is as follows: 1) For each cell, let the cell have a 32 bit mpu with a large amount of local memory (1M dynamic) and just enough ROM on board to recognize a PROLOG kernal. 2) The interconnection medium would be a one dimensional microwave waveguide having an overall bandwidth of, say 100 Ghz to use a nice round number. This medium would be divided into channels of 1 Mhz , for a total of 100,000 channels. 3) Each cell would have 2 adjustable listening center frequencies and 1 adjustable transmitting center frequency. The adjustments would be controlled by each cell under it's own individual software control. 4) Cells would communicate with each other under a distributed contention protocol. Ideally, groups of cells would be clustered together under mutual communication in a process, such that the contention protocol would do the equivalent of segmentation. Does this sound like it makes any sense? Andrew Fine
baker@hpfcla.UUCP (10/21/85)
> I had an idea about creating a systolic machine, but it might not seem to > follow any orthodox rules. > > The way I thought of doing it is as follows: > > 1) For each cell, let the cell have a 32 bit mpu with a large amount of local > memory (1M dynamic) and just enough ROM on board to recognize a PROLOG kernal. > > 2) The interconnection medium would be a one dimensional microwave waveguide > > 3) Each cell would have 2 adjustable listening center frequencies and 1 > adjustable transmitting center frequency. > > 4) Cells would communicate with each other under a distributed contention > protocol. > > Does this sound like it makes any sense? By definition what you propose is not a systolic machine. A systolic machine is: - Few types of simple cells (Simple logic units & a few words of memory) - Data and control flows are simple and regular - Memory I/O only on the boundary cells - Systolic system: data flows from memory in a rhythmic fashion, passing through many PE's before returning to memory, much like blood flows through the heart. References (and good reading): "Why Systolic Architectures?", H.T. Kung, Jan. 1982, Computer "Design of the PSC: A Programmable Systolic Chip", Fisher,Kung,et.al., Proc. of the Third Caltech Conf. on VLSI (also in Sigarch 83 somewhere). Jim Baker hplabs!hpfcla!baker Hewlett-Packard