eugene@ames.UUCP (Eugene Miya) (12/23/85)
> Has anyone ever built a cached vector machine? > > Jeff Bell > ARPA: jbell%tallis.DEC@decwrl.ARPA > UUCP: ....!decwrl!tallis!jbell > Yes, the Japanese machines have some interesting variable length vector schemes which could be called a cache. The Cray-2 also has a "local" 16 K Word memory to replace the B and T registers, but CRI does not use the work "cache." I think it can be consider such. I am supposed to run on a VP-200 later this week. I've got a copy of Alan Smith's cache benchmark for the Cray-2, but the current version of the compiler does not use it. On dhrystones: They suffer many of the same problems of Whetstones, the Loops, the Sieve and so forth. They lack a deep basis in reality. They don't really tell you what's going on. For all you know, whole functions are getting optimized out. Programs are an important blend of I/O as well as memory CPU functions. The people who write benchmarks [myself included] like to think they know what's going on with a machine, but few have any proof their observations are correct. Few people even know what constitutes the contents of a Whetstone [I only learned a year or so ago], a few more can cite the reference, fewer know why the Whetstone is the way it is. Every week, I spend timing measuring something, I find some result that is unexpected. Few people even understand the nature of the system clocks they are dealing with. In someways, benchmarks are like IQ tests [I'm stretching the analogy]: the people who make the most out of them are those who don't write them. The people who do write them typically slink off into a corner [not entirely, true, but gives you something to think about]. I am learning that when you really find things out about machines, you begin to walk on sensitive ground and that people might begin to think they don't want you running on their machines for fear of looking bad in some way. From the Rock of Ages Home for Retired Hackers: --eugene miya NASA Ames Research Center {hplabs,ihnp4,dual,hao,decwrl,allegra}!ames!aurora!eugene emiya@ames-vmsb.ARPA
mat@amdahl.UUCP (Mike Taylor) (12/26/85)
> > Yes, the Japanese machines have some interesting variable length > vector schemes which could be called a cache. The Cray-2 also has > a "local" 16 K Word memory to replace the B and T registers, but > CRI does not use the work "cache." I think it can be consider such. > I am supposed to run on a VP-200 later this week. For what it's worth, Fujitsu VPs do I-fetch from cache. Operand fetch proceeds directly from mainstore via load/store pipe(s). -- Mike Taylor ...!{ihnp4,hplabs,amd,sun}!amdahl!mat [ This may not reflect my opinion, let alone anyone else's. ]